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An Improved Router Design for Reliable On-Chip Networks
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1057/jors.1983.197openalex-snapshot
Probability and Statistics with Reliability, Queueing and Computer Science Applications
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/7298.946457openalex-snapshot
Hot carrier degradation and ESD in submicrometer CMOS technologies: how do they interact?
inferredcites →https://doi.org/10.1109/dsn.2007.8openalex-snapshot
A Framework for Architecture-Level Lifetime Reliability Modeling
inferredcites →https://doi.org/10.1109/hkedm.1999.836404openalex-snapshot
On the oxide thickness dependence of the time-dependent-dielectric-breakdown
inferredcites →https://doi.org/10.1109/hpca.2001.903268openalex-snapshot
A delay model and speculative architecture for pipelined routers
inferredcites →https://doi.org/10.1109/hpca.2006.1598108openalex-snapshot
BulletProof: A Defect~Tolerant CMP Switch Architecture
inferredcites →https://doi.org/10.1109/icecs.2004.1399629openalex-snapshot
Electromigration-dependent parametric yield estimation
inferredcites →https://doi.org/10.1109/icvd.2005.171openalex-snapshot
VLSI design challenges for gigascale integration
inferredcites →https://doi.org/10.1109/iedm.2007.4418976openalex-snapshot
Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS
inferredcites →https://doi.org/10.1109/isca.1995.524546openalex-snapshot
The SPLASH-2 programs: characterization and methodological considerations
inferredcites →https://doi.org/10.1109/isca.2004.1310781openalex-snapshot
The case for lifetime reliability-aware microprocessors
inferredcites →https://doi.org/10.1109/ispass.2009.4919636openalex-snapshot
GARNET: A detailed on-chip network model inside a full-system simulator
inferredcites →https://doi.org/10.1109/micro.2012.15openalex-snapshot
NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures
inferredcites →https://doi.org/10.1109/t-ed.1979.19370openalex-snapshot
Alpha-particle-induced soft errors in dynamic memories
inferredcites →https://doi.org/10.1109/tr.1963.5218202openalex-snapshot
Time to Failure and Availability of Paralleled Systems with Repair
inferredcites →https://doi.org/10.1145/1028176.1006725openalex-snapshot
The Case for Lifetime Reliability-Aware Microprocessors
inferredcites →https://doi.org/10.1145/1150019.1136487openalex-snapshot
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
inferredcites →https://doi.org/10.1145/1999946.1999964openalex-snapshot
Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration
inferredcites →https://doi.org/10.1145/2024724.2024931openalex-snapshot
Enabling system-level modeling of variation-induced faults in networks-on-chips
inferredcites →https://doi.org/10.1147/rd.462.0287openalex-snapshot
CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics
inferredcites →https://doi.org/10.2307/2288237openalex-snapshot
Probability and Statistics With Reliability, Queuing, and Computer Science Applications.
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11227-025-07733-6openalex-snapshot
Simultaneous optimization of network-on-chip to improve reliability and reduce average packet latency considering buffer size constraints
inferred← citeshttps://doi.org/10.1007/s11390-017-1703-5openalex-snapshot
An Efficient Network-on-Chip Router for Dataflow Architecture
inferred← citeshttps://doi.org/10.1016/j.jpdc.2016.03.014openalex-snapshot
Adaptive fault-tolerant architecture and routing algorithm for reliable many-core 3D-NoC systems
inferred← citeshttps://doi.org/10.1016/j.micpro.2016.04.009openalex-snapshot
A low-cost, fault-tolerant and high-performance router architecture for on-chip networks
inferred← citeshttps://doi.org/10.1016/j.vlsi.2016.10.016openalex-snapshot
A high performance reliable NoC router
inferred← citeshttps://doi.org/10.1109/access.2019.2944490openalex-snapshot
Defender: A Low Overhead and Efficient Fault-Tolerant Mechanism for Reliable on-Chip Router
inferred← citeshttps://doi.org/10.1109/aspdac.2016.7428095openalex-snapshot
A High Performance Reliable NoC Router
inferred← citeshttps://doi.org/10.1109/hpcsim.2016.7568320openalex-snapshot
A reliable and high-performance Network-on-Chip router through decoupled resource sharing
inferred← citeshttps://doi.org/10.1109/iccic.2017.8524288openalex-snapshot
A Unique Low Power Network-an-Chip Virtual Channel Router
inferred← citeshttps://doi.org/10.1109/iciiecs.2017.8275885openalex-snapshot
Design of high performance reliable network on chip router
inferred← citeshttps://doi.org/10.1109/lca.2014.2360686openalex-snapshot
A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core Systems
inferred← citeshttps://doi.org/10.1109/mcsoc.2014.36openalex-snapshot
Adaptive Error- and Traffic-Aware Router Architecture for 3D Network-on-Chip Systems
inferred← citeshttps://doi.org/10.1109/tpds.2016.2521641openalex-snapshot
Shield: A Reliable Network-on-Chip Router Architecture for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/vlsi-dat.2019.8741845openalex-snapshot
Design of an Adaptive and Reliable Network on Chip Router Architecture Using FPGA
inferred← citeshttps://doi.org/10.1145/3233986openalex-snapshot
Limit of Hardware Solutions for Self-Protecting Fault-Tolerant NoCs
inferred← citeshttps://doi.org/10.1145/3787109.3815277openalex-snapshot
ReSafe-ViT: A Reconfigurable and Reliable Accelerator for Vision Transformer Inference
inferred← citeshttps://doi.org/10.21203/rs.3.rs-4102834/v1openalex-snapshot
Simultaneous Optimization of Network-on-Chip for Improved Reliability and Reduced Average Packet Latency Considering Buffer Size Constraints
inferred← citeshttps://doi.org/10.22581/muet1982.2004.02openalex-snapshot
Protector: A Permanent Fault Resilient Router Architecture for Network on Chip
inferred← citeshttps://doi.org/10.23919/date.2019.8714869openalex-snapshot
High-performance, energy-efficient, fault-tolerant network-on-chip design using reinforcement learning
inferred← citeshttps://doi.org/10.3233/jhs-200646openalex-snapshot
A new architecture for online error detection and isolation in network on chip
inferred← citeshttps://doi.org/10.3390/jlpea9010011openalex-snapshot
Tolerating Permanent Faults in the Input Port of the Network on Chip Router
inferred← citeshttps://doi.org/10.3390/s20185355openalex-snapshot
Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things
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