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Enabling system-level modeling of variation-induced faults in networks-on-chips
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/s10820-006-9044-7openalex-snapshot
Forbidden pitches in sub-wavelength lithography and their implications on design
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inferredcites →https://doi.org/10.1109/iccad.2006.320152openalex-snapshot
Microarchitecture Parameter Selection To Optimize System Performance Under Process Variation
inferredcites →https://doi.org/10.1109/iccd.2010.5647666openalex-snapshot
SWIFT: A SWing-reduced interconnect for a Token-based Network-on-Chip in 90nm CMOS
inferredcites →https://doi.org/10.1109/ispass.2009.4919636openalex-snapshot
GARNET: A detailed on-chip network model inside a full-system simulator
inferredcites →https://doi.org/10.1109/isqed.2006.91openalex-snapshot
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
inferredcites →https://doi.org/10.1109/isqed.2007.16openalex-snapshot
A Model for Timing Errors in Processors with Parameter Variation
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A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS
inferredcites →https://doi.org/10.1109/micro.2006.37openalex-snapshot
Mitigating the Impact of Process Variations on Processor Register Files and Execution Units
inferredcites →https://doi.org/10.1109/mm.2007.4378783openalex-snapshot
A 5-GHz Mesh Interconnect for a Teraflops Processor
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Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems
inferredcites →https://doi.org/10.1109/tdsc.2008.59openalex-snapshot
On the Effects of Process Variation in Network-on-Chip Architectures
inferredcites →https://doi.org/10.1109/tsm.2007.913186openalex-snapshot
VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
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Statistical reliability analysis under process variation and aging effects
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What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1016/j.jpdc.2016.12.019openalex-snapshot
Architecture level analysis for process variation in synchronous and asynchronous Networks-on-Chip
inferred← citeshttps://doi.org/10.1016/j.mejo.2015.01.004openalex-snapshot
Process variability-induced NoC link failure: A probabilistic model
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Variability-tolerant routing algorithms for Networks-on-Chip
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Towards fault adaptive routing in metasurface controller networks
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On Covering Structural Defects in NoCs by Functional Tests
inferred← citeshttps://doi.org/10.1109/cisp-bmei.2016.7852833openalex-snapshot
Research on network fault tolerance method on chip
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Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning
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RETUNES: Reliable and Energy-Efficient Network-on-Chip Architecture
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Redundancy and ECC mechanisms to improve energy efficiency of on-die interconnects
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An Improved Router Design for Reliable On-Chip Networks
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FILA: Fault-Model for Interconnection Links in Application-Specific Network-on-Chip Design
inferred← citeshttps://doi.org/10.1109/lca.2014.2360686openalex-snapshot
A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core Systems
inferred← citeshttps://doi.org/10.1109/micro.2012.15openalex-snapshot
NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures
inferred← citeshttps://doi.org/10.1109/micro.2012.34openalex-snapshot
Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance
inferred← citeshttps://doi.org/10.1109/micro.2016.7783734openalex-snapshot
Dynamic error mitigation in NoCs using intelligent prediction techniques
inferred← citeshttps://doi.org/10.1109/nocs.2014.7008759openalex-snapshot
FMEA-based analysis of a Network-on-Chip for mixed-critical systems
inferred← citeshttps://doi.org/10.1109/pact.2011.61openalex-snapshot
ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment
inferred← citeshttps://doi.org/10.1109/socc.2017.8226065openalex-snapshot
System-level simulator for process variation influenced synchronous and asynchronous NoCs
inferred← citeshttps://doi.org/10.1109/tc.2015.2439276openalex-snapshot
Fault-Aware Load-Balancing Routing for 2D-Mesh and Torus On-Chip Network Topologies
inferred← citeshttps://doi.org/10.1109/tcad.2017.2664066openalex-snapshot
Runtime Techniques to Mitigate Soft Errors in Network-on-Chip (NoC) Architectures
inferred← citeshttps://doi.org/10.1109/tetc.2022.3147407openalex-snapshot
HREN: A Hybrid Reliable and Energy-Efficient Network-on-Chip Architecture
inferred← citeshttps://doi.org/10.1109/tvlsi.2017.2736004openalex-snapshot
A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model
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A systematic methodology to develop resilient cache coherence protocols
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A survey and taxonomy of on-chip monitoring of multicore systems-on-chip
inferred← citeshttps://doi.org/10.1145/2522968.2522976openalex-snapshot
Methods for fault tolerance in networks-on-chip
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Accurate System-level TSV-to-TSV Capacitive Coupling Fault Model for 3D-NoC
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Multi-Layer Test and Diagnosis for Dependable NoCs
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Clustered Networks-on-Chip: Simulation and Performance Evaluation
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On-Chip Networks, Second Edition
inferred← citeshttps://doi.org/10.23919/date.2019.8714869openalex-snapshot
High-performance, energy-efficient, fault-tolerant network-on-chip design using reinforcement learning
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IDFT: An Intermediate Node Based Deterministic Fault Tolerant Routing in 2D Mesh
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Enabling Simultaneously Bi-Directional TSV Signaling for Energy and Area Efficient 3D-ICs
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Contributions aux processeurs multi-coeurs massivement parallèles en technologie en rupture : routage tolérant aux fautes de réseau d'interconnexion et auto-adaptabilité des applications
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