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NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-58429-3_41openalex-snapshot
The Reliable Router: A reliable and high-performance communication substrate for parallel computers
inferredcites →https://doi.org/10.1016/s0038-1101(02)00151-xopenalex-snapshot
Interplay of voltage and temperature acceleration of oxide breakdown for ultra-thin gate oxides
inferredcites →https://doi.org/10.1109/71.605766openalex-snapshot
A theory of fault-tolerant routing in wormhole networks
inferredcites →https://doi.org/10.1109/aspdac.2003.1195021openalex-snapshot
Towards on-chip fault-tolerant communication
inferredcites →https://doi.org/10.1109/date.2007.364618openalex-snapshot
Using the Inter- and Intra-Switch Regularity in NoC Switch Testing
inferredcites →https://doi.org/10.1109/date.2009.5090627openalex-snapshot
A highly resilient routing algorithm for fault-tolerant NoCs
inferredcites →https://doi.org/10.1109/date.2011.5763109openalex-snapshot
Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture
inferredcites →https://doi.org/10.1109/date.2011.5763112openalex-snapshot
ReliNoC: A reliable network for priority-based on-chip communication
inferredcites →https://doi.org/10.1109/dsn.2006.35openalex-snapshot
Exploring Fault-Tolerant Network-on-Chip Architectures
inferredcites →https://doi.org/10.1109/hpca.2001.903268openalex-snapshot
A delay model and speculative architecture for pipelined routers
inferredcites →https://doi.org/10.1109/hpca.2006.1598108openalex-snapshot
BulletProof: A Defect~Tolerant CMP Switch Architecture
inferredcites →https://doi.org/10.1109/iccd.2007.4601881openalex-snapshot
A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS
inferredcites →https://doi.org/10.1109/ispass.2009.4919636openalex-snapshot
GARNET: A detailed on-chip network model inside a full-system simulator
inferredcites →https://doi.org/10.1109/isscc.2012.6176876openalex-snapshot
A 22nm IA multi-CPU and GPU System-on-Chip
inferredcites →https://doi.org/10.1109/jssc.2007.910957openalex-snapshot
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS
inferredcites →https://doi.org/10.1109/jssc.2010.2079450openalex-snapshot
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling
inferredcites →https://doi.org/10.1109/micro.2004.24openalex-snapshot
Microarchitecture and Design Challenges for Gigascale Integration
inferredcites →https://doi.org/10.1109/micro.2007.18openalex-snapshot
Argus: Low-Cost, Comprehensive Error Detection in Simple Cores
inferredcites →https://doi.org/10.1109/micro.2007.8openalex-snapshot
40th Annual IEEE/ACM International Symposium on Microarchitecture - Table of Contents
inferredcites →https://doi.org/10.1109/nocs.2007.1openalex-snapshot
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study
inferredcites →https://doi.org/10.1109/nocs.2008.4492721openalex-snapshot
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip
inferredcites →https://doi.org/10.1109/nocs.2009.5071441openalex-snapshot
Fault-tolerant architecture and deflection routing for degradable NoC switches
inferredcites →https://doi.org/10.1109/nocs.2010.12openalex-snapshot
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing
inferredcites →https://doi.org/10.1109/pact.2011.61openalex-snapshot
ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment
inferredcites →https://doi.org/10.1109/tc.2008.95openalex-snapshot
Immunet: Dependable Routing for Interconnection Networks with Arbitrary Topology
inferredcites →https://doi.org/10.1109/tcad.2010.2041851openalex-snapshot
Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks-on-Chip
inferredcites →https://doi.org/10.1109/tcad.2010.2048399openalex-snapshot
Fault Tolerant Network on Chip Switching With Graceful Performance Degradation
inferredcites →https://doi.org/10.1109/tdsc.2008.59openalex-snapshot
On the Effects of Process Variation in Network-on-Chip Architectures
inferredcites →https://doi.org/10.1109/test.2011.6139156openalex-snapshot
End-to-end error correction and online diagnosis for on-chip networks
inferredcites →https://doi.org/10.1109/vts.2012.6231078openalex-snapshot
Comprehensive online defect diagnosis in on-chip networks
inferredcites →https://doi.org/10.1145/1119772.1119817openalex-snapshot
Towards on-chip fault-tolerant communication
inferredcites →https://doi.org/10.1145/1146909.1147124openalex-snapshot
A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip
inferredcites →https://doi.org/10.1145/1150019.1136487openalex-snapshot
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
inferredcites →https://doi.org/10.1145/1555754.1555781openalex-snapshot
A case for bufferless routing in on-chip networks
inferredcites →https://doi.org/10.1145/1555815.1555781openalex-snapshot
A case for bufferless routing in on-chip networks
inferredcites →https://doi.org/10.1145/1999946.1999965openalex-snapshot
A distributed and topology-agnostic approach for on-line NoC testing
inferredcites →https://doi.org/10.1145/2000064.2000096openalex-snapshot
An abacus turn model for time/space-efficient reconfigurable routing
inferredcites →https://doi.org/10.1145/2024724.2024931openalex-snapshot
Enabling system-level modeling of variation-induced faults in networks-on-chips
inferredcites →https://doi.org/10.1145/2155620.2155668openalex-snapshot
Formally enhanced runtime verification to ensure NoC functional correctness
inferredcites →https://doi.org/10.1145/237090.237140openalex-snapshot
The case for a single-chip multiprocessor
inferredcites →https://doi.org/10.1145/363235.363259openalex-snapshot
An axiomatic basis for computer programming
inferredcites →https://doi.org/10.5555/1266366.1266443openalex-snapshot
Using the inter- and intra-switch regularity in NoC switch testing
inferredcites →https://doi.org/10.5555/1874620.1874628openalex-snapshot
A highly resilient routing algorithm for fault-tolerant NoCs
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-69131-8_17openalex-snapshot
Securing 3D NoCs from Hardware Trojan Attacks
inferred← citeshttps://doi.org/10.1007/978-3-030-92525-3_6openalex-snapshot
Fault-Tolerant Neuromorphic System Design
inferred← citeshttps://doi.org/10.1007/978-3-319-16214-0_16openalex-snapshot
Survey on Real-Time Network-on-Chip Architectures
inferred← citeshttps://doi.org/10.1007/978-3-319-31596-6_11openalex-snapshot
Adroit Use of Dark Silicon for Power, Performance and Reliability Optimisation of NoCs
inferred← citeshttps://doi.org/10.1007/978-3-319-68511-3_12openalex-snapshot
Hardware Obfuscation Methods for Hardware Trojan Prevention and Detection
inferred← citeshttps://doi.org/10.1007/978-3-319-91962-1_1openalex-snapshot
The HARPA Approach to Ensure Dependable Performance
inferred← citeshttps://doi.org/10.1007/978-3-319-91962-1_9openalex-snapshot
Monitor and Knob Techniques in Network-on-Chip Architectures
inferred← citeshttps://doi.org/10.1007/s11227-016-1951-0openalex-snapshot
A low-overhead soft–hard fault-tolerant architecture, design and management scheme for reliable high-performance many-core 3D-NoC systems
inferred← citeshttps://doi.org/10.1007/s41635-022-00129-5openalex-snapshot
Network-on-Chip Trust Validation Using Security Assertions
inferred← citeshttps://doi.org/10.1016/j.jpdc.2017.06.014openalex-snapshot
Mitigation of Hardware Trojan based Denial-of-Service attack for secure NoCs
inferred← citeshttps://doi.org/10.1016/j.micpro.2016.04.009openalex-snapshot
A low-cost, fault-tolerant and high-performance router architecture for on-chip networks
inferred← citeshttps://doi.org/10.1016/j.micpro.2016.05.004openalex-snapshot
A runtime fault-tolerant routing algorithm based on region flooding in NoCs
inferred← citeshttps://doi.org/10.1016/j.micpro.2018.01.005openalex-snapshot
Abacus turn model-based routing for NoC interconnects with switch or link failures
inferred← citeshttps://doi.org/10.1016/j.microrel.2014.06.008openalex-snapshot
Accelerated assessment of fine-grain AVF in NoC using a Multi-Cell Upsets considered fault injection
inferred← citeshttps://doi.org/10.1016/j.vlsi.2016.06.008openalex-snapshot
A hardened network-on-chip design using runtime hardware Trojan mitigation methods
inferred← citeshttps://doi.org/10.1016/j.vlsi.2016.10.016openalex-snapshot
A high performance reliable NoC router
inferred← citeshttps://doi.org/10.1016/j.vlsi.2025.102603openalex-snapshot
NeSTAR: Hardware Trojans and its mitigation strategy in NoC routers
inferred← citeshttps://doi.org/10.1109/access.2019.2944490openalex-snapshot
Defender: A Low Overhead and Efficient Fault-Tolerant Mechanism for Reliable on-Chip Router
inferred← citeshttps://doi.org/10.1109/access.2021.3100540openalex-snapshot
A Survey on the Security of Wired, Wireless, and 3D Network-on-Chips
inferred← citeshttps://doi.org/10.1109/aspdac.2016.7428095openalex-snapshot
A High Performance Reliable NoC Router
inferred← citeshttps://doi.org/10.1109/ats.2016.37openalex-snapshot
Reliability Assessment and Quantitative Evaluation of Soft-Error Resilient 3D Network-on-Chip Systems
inferred← citeshttps://doi.org/10.1109/bec.2014.7320560openalex-snapshot
Extended checkers for Logic-Based Distributed Routing in Network-on-Chips
inferred← citeshttps://doi.org/10.1109/ddecs.2017.7934565openalex-snapshot
From online fault detection to fault management in Network-on-Chips: A ground-up approach
inferred← citeshttps://doi.org/10.1109/dsd.2015.15openalex-snapshot
A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835942openalex-snapshot
QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers
inferred← citeshttps://doi.org/10.1109/hpcc-dss-smartcity-dependsys57074.2022.00195openalex-snapshot
HCER: A High Cost-Effectiveness Multi-Bit Fault-Tolerant NoC Router
inferred← citeshttps://doi.org/10.1109/icawst.2015.7314025openalex-snapshot
Soft-error resilient 3D Network-on-Chip router
inferred← citeshttps://doi.org/10.1109/icccn.2017.8038407openalex-snapshot
Dynamically Reconfigurable Architecture for Fault-Tolerant 2D Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/iccd.2013.6657052openalex-snapshot
Energy-efficient Runtime Adaptive Scrubbing in fault-tolerant Network-on-Chips (NoCs) architectures
inferred← citeshttps://doi.org/10.1109/iccsn.2015.7296140openalex-snapshot
A low cost serious failure tolerance solution in unreliable NoCs
inferred← citeshttps://doi.org/10.1109/ipdps.2014.39openalex-snapshot
An Improved Router Design for Reliable On-Chip Networks
inferred← citeshttps://doi.org/10.1109/ipdps.2016.59openalex-snapshot
Mitigation of Denial of Service Attack with Hardware Trojans in NoC Architectures
inferred← citeshttps://doi.org/10.1109/iscas.2017.8050828openalex-snapshot
Non-blocking BIST for continuous reliability monitoring of Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/iscas45731.2020.9180583openalex-snapshot
Invariance Checking Based Trojan Detection Method for Three-Dimensional Integrated Circuits
inferred← citeshttps://doi.org/10.1109/isqed.2019.8697766openalex-snapshot
Resilient Reorder Buffer Design for Network-on-Chip
inferred← citeshttps://doi.org/10.1109/isvlsi.2015.33openalex-snapshot
Design of Fault-Tolerant and Reliable Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/jetcas.2020.2974236openalex-snapshot
TSV Antennas for Multi-Band Wireless Communication
inferred← citeshttps://doi.org/10.1109/jiot.2024.3509525openalex-snapshot
A Network-Coding-Based Functional Test Method for Routers in 3-D Mesh NoCs
inferred← citeshttps://doi.org/10.1109/les.2013.2283740openalex-snapshot
Hybrid Fault Detection for Adaptive NoC
inferred← citeshttps://doi.org/10.1109/micro.2016.7783734openalex-snapshot
Dynamic error mitigation in NoCs using intelligent prediction techniques
inferred← citeshttps://doi.org/10.1109/mwscas60917.2024.10658715openalex-snapshot
NoC-Armor: Leveraging Quantitative Analysis for Enhanced Security
inferred← citeshttps://doi.org/10.1109/pdp.2015.87openalex-snapshot
A Routing-Level Solution for Fault Detection, Masking, and Tolerance in NoCs
inferred← citeshttps://doi.org/10.1109/recosoc.2015.7238079openalex-snapshot
Automated minimization of concurrent online checkers for Network-on-Chips
inferred← citeshttps://doi.org/10.1109/recosoc.2016.7533905openalex-snapshot
Online reconfigurable routing method for handling link failures in NoC-based MPSoCs
inferred← citeshttps://doi.org/10.1109/samos.2015.7363685openalex-snapshot
HARPA: Solutions for dependable performance under physically induced performance variability
inferred← citeshttps://doi.org/10.1109/sbac-pad.2013.32openalex-snapshot
Tackling Permanent Faults in the Network-on-Chip Router Pipeline
inferred← citeshttps://doi.org/10.1109/sbcci50935.2020.9189905openalex-snapshot
Multiple-objective Management based on a Distributed SDN Architecture for Many-cores
inferred← citeshttps://doi.org/10.1109/slip.2019.8771331openalex-snapshot
FSNoC: Safe Network-on-Chip Design with Packet Level Lock Stepping
inferred← citeshttps://doi.org/10.1109/socc.2015.7406933openalex-snapshot
Fault-resilient routing unit in NoCs
inferred← citeshttps://doi.org/10.1109/socc.2016.7905497openalex-snapshot
ERFAN: Efficient reconfigurable fault-tolerant deflection routing algorithm for 3-D Network-on-Chip
inferred← citeshttps://doi.org/10.1109/ssci.2018.8628839openalex-snapshot
Scalable Bio-inspired Fault Detection, Isolation and Recovery in NoCs
inferred← citeshttps://doi.org/10.1109/tc.2015.2401013openalex-snapshot
Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures
inferred← citeshttps://doi.org/10.1109/tc.2015.2479586openalex-snapshot
Resource Conscious Diagnosis and Reconfiguration for NoC Permanent Faults
inferred← citeshttps://doi.org/10.1109/tc.2015.2489216openalex-snapshot
Non-Blocking Testing for Network-on-Chip
inferred← citeshttps://doi.org/10.1109/tc.2018.2865948openalex-snapshot
Efficient Design-for-Test Approach for Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/tc.2020.2991749openalex-snapshot
ECDR2: Error Corrector and Detector Relocation Router for Network-on-Chip
inferred← citeshttps://doi.org/10.1109/tc.2024.3457732openalex-snapshot
Component Dependencies Based Network-on-Chip Test
inferred← citeshttps://doi.org/10.1109/tcad.2017.2664066openalex-snapshot
Runtime Techniques to Mitigate Soft Errors in Network-on-Chip (NoC) Architectures
inferred← citeshttps://doi.org/10.1109/tetc.2016.2597799openalex-snapshot
An Energy-Efficient NoC Router with Adaptive Fault-Tolerance Using Channel Slicing and On-Demand TMR
inferred← citeshttps://doi.org/10.1109/tetc.2021.3136028openalex-snapshot
MigSpike: A Migration Based Algorithms and Architecture for Scalable Robust Neuromorphic Systems
inferred← citeshttps://doi.org/10.1109/tvlsi.2014.2305335openalex-snapshot
Wearout Resilience in NoCs Through an Aging Aware Adaptive Routing Algorithm
inferred← citeshttps://doi.org/10.1109/tvlsi.2017.2736004openalex-snapshot
A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model
inferred← citeshttps://doi.org/10.1109/tvlsi.2019.2948878openalex-snapshot
TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems
inferred← citeshttps://doi.org/10.1109/vlsi-dat.2019.8741845openalex-snapshot
Design of an Adaptive and Reliable Network on Chip Router Architecture Using FPGA
inferred← citeshttps://doi.org/10.1145/2656075.2656100openalex-snapshot
Tackling QoS-induced aging in exascale systems through agile path selection
inferred← citeshttps://doi.org/10.1145/2786572.2788713openalex-snapshot
A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers
inferred← citeshttps://doi.org/10.1145/2818362.2818372openalex-snapshot
Security Challenges in ManyCore Embedded Systems based on Networks-on-Chip (NoCs)
inferred← citeshttps://doi.org/10.1145/2902961.2903032openalex-snapshot
Secure Model Checkers for Network-on-Chip (NoC) Architectures
inferred← citeshttps://doi.org/10.1145/2930670openalex-snapshot
An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures
inferred← citeshttps://doi.org/10.1145/3267419.3267423openalex-snapshot
Traffic-aware reconfigurable architecture for fault-tolerant 2D mesh NoCs
inferred← citeshttps://doi.org/10.1145/3316781.3317851openalex-snapshot
Lightweight Mitigation of Hardware Trojan Attacks in NoC-based Manycore Computing
inferred← citeshttps://doi.org/10.1145/3450964openalex-snapshot
A Survey of Network-on-Chip Security Attacks and Countermeasures
inferred← citeshttps://doi.org/10.1145/3633461openalex-snapshot
Coherence Attacks and Countermeasures in Interposer-based Chiplet Systems
inferred← citeshttps://doi.org/10.2200/s00772ed1v01y201704cac040openalex-snapshot
On-Chip Networks, Second Edition
inferred← citeshttps://doi.org/10.22581/muet1982.2004.02openalex-snapshot
Protector: A Permanent Fault Resilient Router Architecture for Network on Chip
inferred← citeshttps://doi.org/10.26076/027f-6b3eopenalex-snapshot
Design of Reliable and Secure Network-On-Chip Architectures
inferred← citeshttps://doi.org/10.26599/tst.2019.9010039openalex-snapshot
Fault-tolerant design for data efficient retransmission in WiNoC
inferred← citeshttps://doi.org/10.3390/electronics9020342openalex-snapshot
NoCGuard: A Reliable Network-on-Chip Router Architecture
inferred← citeshttps://doi.org/10.3390/electronics9111783openalex-snapshot
Savior: A Reliable Fault Resilient Router Architecture for Network-on-Chip
inferred← citeshttps://doi.org/10.3390/s19245416openalex-snapshot
Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design
inferred← citeshttps://doi.org/10.3390/s20185355openalex-snapshot
Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things
inferred← citeshttps://doi.org/10.48550/arxiv.1601.07089openalex-snapshot
Holistic Approach for Fault-Tolerant Network-on-Chip based Many-Core Systems
inferred← citeshttps://doi.org/10.48550/arxiv.1702.02313openalex-snapshot
FASHION: Fault-Aware Self-Healing Intelligent On-chip Network
inferred← citeshttps://doi.org/10.48550/arxiv.2006.11025openalex-snapshot
Design of a Near-Ideal Fault-Tolerant Routing Algorithm for Network-on-Chip-Based Multicores
inferred← citeshttps://doi.org/10.5555/3195638.3195675openalex-snapshot
Dynamic error mitigation in NoCs using intelligent prediction techniques
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