On the public citation graph
Balancing On-Chip Network Latency in Multi-application Mapping for Chip-Multiprocessors
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/nav.20053openalex-snapshot
The Hungarian method for the assignment problem
inferredcites →https://doi.org/10.1002/nav.3800020109openalex-snapshot
The Hungarian method for the assignment problem
inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot
Simics: A full system simulation platform
inferredcites →https://doi.org/10.1109/date.2004.1269002openalex-snapshot
Bandwidth-constrained mapping of cores onto NoC architectures
inferredcites →https://doi.org/10.1109/date.2006.244007openalex-snapshot
A Methodology for Mapping Multiple Use-Cases onto Networks on Chips
inferredcites →https://doi.org/10.1109/ddecs.2008.4538763openalex-snapshot
Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip
inferredcites →https://doi.org/10.1109/hpca.2005.10openalex-snapshot
Chip Multithreading: Opportunities and Challenges
inferredcites →https://doi.org/10.1109/ispass.2009.4919636openalex-snapshot
GARNET: A detailed on-chip network model inside a full-system simulator
inferredcites →https://doi.org/10.1109/isscc.2010.5434077openalex-snapshot
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS
inferredcites →https://doi.org/10.1109/l-ca.2011.1openalex-snapshot
Fairness Metrics for Multi-Threaded Processors
inferredcites →https://doi.org/10.1109/micro.2006.25openalex-snapshot
Fairness and Throughput in Switch on Event Multithreading
inferredcites →https://doi.org/10.1109/micro.2006.49openalex-snapshot
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches
inferredcites →https://doi.org/10.1109/micro.2010.18openalex-snapshot
Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs
inferredcites →https://doi.org/10.1109/nocs.2012.31openalex-snapshot
DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling
inferredcites →https://doi.org/10.1145/1084834.1084857openalex-snapshot
A unified approach to constrained mapping and routing on network-on-chip architectures
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/1119772.1119818openalex-snapshot
Energy-aware mapping for tile-based NoC architectures under performance constraints
inferredcites →https://doi.org/10.1145/1391469.1391628openalex-snapshot
Application mapping for chip multiprocessors
inferredcites →https://doi.org/10.1145/1669112.1669150openalex-snapshot
Application-aware prioritization mechanisms for on-chip networks
inferredcites →https://doi.org/10.1145/1735970.1736058openalex-snapshot
Fairness via source throttling
inferredcites →https://doi.org/10.1145/1735971.1736058openalex-snapshot
Fairness via source throttling
inferredcites →https://doi.org/10.5555/968879.969207openalex-snapshot
Bandwidth-constrained mapping of cores onto NoC architectures
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-981-15-8135-9_10openalex-snapshot
Network-on-Chip Aware Task Mappings
inferred← citeshttps://doi.org/10.1007/s11227-022-04444-0openalex-snapshot
A multi-application approach for synthesizing custom network-on-chips
inferred← citeshttps://doi.org/10.1007/s41870-023-01542-xopenalex-snapshot
Contention-free dynamic task scheduling approach for network-on-chip based quad-core systems
inferred← citeshttps://doi.org/10.1016/j.sysarc.2018.10.003openalex-snapshot
A permanent fault tolerant dynamic task allocation approach for Network-on-Chip based multicore systems
inferred← citeshttps://doi.org/10.1016/j.sysarc.2019.08.002openalex-snapshot
Dynamic Task Mapping and Scheduling with Temperature-Awareness on Network-on-Chip based Multicore Systems
inferred← citeshttps://doi.org/10.1177/10692509261477252openalex-snapshot
Deterministic population initialization for multi-objective mapping of multiple applications in network-on-chip-based many-core systems
inferred← citeshttps://doi.org/10.3390/app12063163openalex-snapshot
An Efficient Algorithm for Mapping Deep Learning Applications on the NoC Architecture
inferred← citeshttps://doi.org/10.3390/mi12060613openalex-snapshot
A Multi-Phase Based Multi-Application Mapping Approach for Many-Core Networks-on-Chip
inferred← citeshttps://doi.org/10.5555/2755753.2757100openalex-snapshot
TAPP: temperature-aware application mapping for NoC-based many-core processors
inferred← citeshttps://doi.org/10.5772/intechopen.97341openalex-snapshot
Design and Optimization of Networks-on-Chip
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