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Fly-Over: A Light-Weight Distributed Power-Gating Mechanism for Energy-Efficient Networks-on-Chip
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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A new theory of deadlock-free adaptive routing in wormhole networks
inferredcites →https://doi.org/10.1109/hpca.2001.903268openalex-snapshot
A delay model and speculative architecture for pipelined routers
inferredcites →https://doi.org/10.1109/hpca.2011.5749737openalex-snapshot
A case for guarded power gating for multi-core processors
inferredcites →https://doi.org/10.1109/hpca.2013.6522345openalex-snapshot
Energy-efficient interconnect via Router Parking
inferredcites →https://doi.org/10.1109/hpca.2015.7056048openalex-snapshot
Power punch: Towards non-blocking power-gating of NoC routers
inferredcites →https://doi.org/10.1109/iccad.2005.1560072openalex-snapshot
Application-specific network-on-chip architecture customization via long-range link insertion
inferredcites →https://doi.org/10.1109/iccd.2004.1347970openalex-snapshot
Design-space exploration of power-aware on/off interconnection networks
inferredcites →https://doi.org/10.1109/ispass.2013.6557149openalex-snapshot
A detailed and flexible cycle-accurate Network-on-Chip simulator
inferredcites →https://doi.org/10.1109/isqed.2009.4810399openalex-snapshot
Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs)
inferredcites →https://doi.org/10.1109/jproc.1998.658762openalex-snapshot
Cramming More Components Onto Integrated Circuits
inferredcites →https://doi.org/10.1109/jssc.1974.1050511openalex-snapshot
Design of ion-implanted MOSFET's with very small physical dimensions
inferredcites →https://doi.org/10.1109/jssc.2010.2079450openalex-snapshot
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling
inferredcites →https://doi.org/10.1109/l-ca.2009.46openalex-snapshot
Power Management of Datacenter Workloads Using Per-Core Power Gating
inferredcites →https://doi.org/10.1109/micro.2012.33openalex-snapshot
NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers
inferredcites →https://doi.org/10.1109/mm.2002.997877openalex-snapshot
The Raw microprocessor: a computational fabric for software circuits and general-purpose programs
inferredcites →https://doi.org/10.1109/mm.2007.4378783openalex-snapshot
A 5-GHz Mesh Interconnect for a Teraflops Processor
inferredcites →https://doi.org/10.1109/nocs.2007.6openalex-snapshot
A Power and Energy Exploration of Network-on-Chip Architectures
inferredcites →https://doi.org/10.1109/nocs.2010.16openalex-snapshot
Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs
inferredcites →https://doi.org/10.1109/nocs.2012.31openalex-snapshot
DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling
inferredcites →https://doi.org/10.1109/sbac-pad.2013.10openalex-snapshot
Dynamic Selective Devectorization for Efficient Power Gating of SIMD Units in a HW/SW Co-Designed Environment
inferredcites →https://doi.org/10.1109/tc.2012.273openalex-snapshot
Exploiting Emergence in On-Chip Interconnects
inferredcites →https://doi.org/10.1109/tvlsi.2006.878263openalex-snapshot
"It's a small world after all": NoC performance optimization via long-range link insertion
inferredcites →https://doi.org/10.1145/1186736.1186737openalex-snapshot
SPEC CPU2006 benchmark descriptions
inferredcites →https://doi.org/10.1145/1629911.1629926openalex-snapshot
Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating
inferredcites →https://doi.org/10.1145/2593069.2593187openalex-snapshot
Power-Aware NoCs through Routing and Topology Reconfiguration
inferredcites →https://doi.org/10.1145/871506.871531openalex-snapshot
Leakage power modeling and optimization in interconnection networks
inferredcites →https://doi.org/10.1145/871506.871620openalex-snapshot
Energy optimization techniques in cluster interconnects
inferredcites →https://doi.org/10.5555/2523721.2523746openalex-snapshot
SMT-centric power-aware thread placement in chip multiprocessors
inferredcites →https://doi.org/10.7551/mitpress/12274.003.0027openalex-snapshot
Cramming More Components onto Integrated Circuits (1965)
inferredcites →https://doi.org/10.7873/date.2015.0694openalex-snapshot
Malleable NoC: Dark Silicon Inspired Adaptable Network-on-Chip
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Architectures for Self-Powered Edge Intelligence
inferred← citeshttps://doi.org/10.1007/978-981-97-9314-3_9openalex-snapshot
Architectures for Self-Powered Edge Intelligence
inferred← citeshttps://doi.org/10.1109/dsd.2019.00027openalex-snapshot
EVC-Based Power Gating Approach to Achieve Low-Power and High Performance NoC
inferred← citeshttps://doi.org/10.1109/hpcc/smartcity/dss.2019.00279openalex-snapshot
A Dynamic Bypass Approach to Realize Power Efficient Network-on-Chip
inferred← citeshttps://doi.org/10.1109/ised.2018.8704027openalex-snapshot
Non-blocking Gated Buffers for Energy Efficient on-chip Interconnects in the era of Dark Silicon
inferred← citeshttps://doi.org/10.1109/tc.2020.3033163openalex-snapshot
A Voting Approach for Adaptive Network-on-Chip Power-Gating
inferred← citeshttps://doi.org/10.1109/tcad.2020.3007555openalex-snapshot
Investigating Frequency Scaling, Nonvolatile, and Hybrid Memory Technologies for On-Chip Routers to Support the Era of Dark Silicon
inferred← citeshttps://doi.org/10.1109/tetc.2020.3003496openalex-snapshot
Agile: A Learning-Enabled Power and Performance-Efficient Network-on-Chip Design
inferred← citeshttps://doi.org/10.1142/s021812662450172xopenalex-snapshot
Applying SMART-Based Power Gating Approach in NoC System
inferred← citeshttps://doi.org/10.1145/3695874openalex-snapshot
F-Bypass: A Low-Power Network-on-Chip Design Utilizing Bypass to Improve Network Connectivity
inferred← citeshttps://doi.org/10.21203/rs.3.rs-4339632/v1openalex-snapshot
UBMR:A low-power and low-area multicastrouter with unified buffers forNetwork-on-Chips
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