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NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers
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Outgoing claims: the papers this work cites, builds on, or argues with.
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Benefits and costs of power-gating technique
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Cubic Ring Networks: A Polymorphic Topology for Network-on-Chip
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A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling
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Energy optimization techniques in cluster interconnects
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A Lightweight Fault-Tolerant Mechanism for Network-on-Chip
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Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks
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Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs
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A low latency router supporting adaptivity for on-chip interconnects
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A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
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Dynamic power gating with quality guarantees
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Energy optimization techniques in cluster interconnects
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Investigation of monitoring techniques for self-adaptive integrated systems
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Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.