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Slackened Memory Dependence Enforcement: Combining Opportunistic Forwarding with Decoupled Verification
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/hpca.2004.10011openalex-snapshot
Understanding Scheduling Replay Schemes
inferredcites →https://doi.org/10.1109/hpca.2006.1598133openalex-snapshot
Software-Hardware Cooperative Memory Disambiguation
inferredcites →https://doi.org/10.1109/isca.2004.1310766openalex-snapshot
Memory ordering: a value-based approach
inferredcites →https://doi.org/10.1109/isca.2005.46openalex-snapshot
Scalable Load and Store Processing in Latency Tolerant Processors
inferredcites →https://doi.org/10.1109/isca.2005.47openalex-snapshot
Store Buffer Design in First-Level Multibanked Data Caches
inferredcites →https://doi.org/10.1109/isca.2005.48openalex-snapshot
Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization
inferredcites →https://doi.org/10.1109/micro.1997.645814openalex-snapshot
Streamlining inter-operation memory communication via data dependence prediction
inferredcites →https://doi.org/10.1109/micro.1999.809458openalex-snapshot
DIVA: a reliable substrate for deep submicron microarchitecture design
inferredcites →https://doi.org/10.1109/micro.2003.1253244openalex-snapshot
Scalable hardware memory disambiguation for high ILP processors
inferredcites →https://doi.org/10.1109/micro.2003.1253245openalex-snapshot
Reducing design complexity of the load/store queue
inferredcites →https://doi.org/10.1109/micro.2003.1253246openalex-snapshot
Checkpoint processing and recovery: towards scalable large instruction window processors
inferredcites →https://doi.org/10.1109/micro.2005.10openalex-snapshot
Address-Indexed Memory Disambiguation and Store-to-Load Forwarding
inferredcites →https://doi.org/10.1109/micro.2005.29openalex-snapshot
Scalable Store-Load Forwarding via Store Queue Index Prediction
inferredcites →https://doi.org/10.1145/268806.268810openalex-snapshot
The SimpleScalar tool set, version 2.0
inferredcites →https://doi.org/10.1145/859618.859627openalex-snapshot
Banked multiported register files for high-frequency superscalar microprocessors
inferredcites →https://doi.org/10.1147/rd.502.0287openalex-snapshot
Decomposing the load-store queue by function for power reduction and scalability
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1109/hpca.2008.4658628openalex-snapshot
Branch-mispredict level parallelism (BLP) for control independence
inferred← citeshttps://doi.org/10.1109/iccd.2012.6378654openalex-snapshot
SOLE: Speculative one-cycle load execution with scalability, high-performance and energy-efficiency
inferred← citeshttps://doi.org/10.1109/isca.2008.39openalex-snapshot
Fetch-Criticality Reduction through Control Independence
inferred← citeshttps://doi.org/10.1109/lpe.2006.4271848openalex-snapshot
Substituting Associative Load Queue with Simple Hash Tables in Out-of-Order Microprocessors
inferred← citeshttps://doi.org/10.1109/micro.2006.21openalex-snapshot
DMDC: Delayed Memory Dependence Checking through Age-Based Filtering
inferred← citeshttps://doi.org/10.1109/micro.2006.39openalex-snapshot
NoSQ: Store-Load Communication without a Store Queue
inferred← citeshttps://doi.org/10.1109/mm.2007.17openalex-snapshot
NoSQ: Store-Load Communication without a Store Queue
inferred← citeshttps://doi.org/10.1109/tc.2008.146openalex-snapshot
Replacing Associative Load Queues: A Timing-Centric Approach
inferred← citeshttps://doi.org/10.1109/tc.2010.131openalex-snapshot
Macro Data Load: An Efficient Mechanism for Enhancing Loaded Data Reuse
inferred← citeshttps://doi.org/10.1145/1165573.1165637openalex-snapshot
Substituting associative load queue with simple hash tables in out-of-order microprocessors
inferred← citeshttps://doi.org/10.1145/1394608.1382170openalex-snapshot
Fetch-Criticality Reduction through Control Independence
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95043openalex-snapshot
Design of a distributed memory unit for clustered microarchitectures
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