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Address-Indexed Memory Disambiguation and Store-to-Load Forwarding

https://doi.org/10.1109/micro.2005.10

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/12.509907openalex-snapshot

ARB: a hardware mechanism for dynamic reordering of memory references

inferredcites →https://doi.org/10.1109/40.491460openalex-snapshot

The Mips R10000 superscalar microprocessor

inferredcites →https://doi.org/10.1109/cmpcon.1997.584667openalex-snapshot

The Alpha 21264: a 500 MHz out-of-order execution microprocessor

inferredcites →https://doi.org/10.1109/hipc.1996.565856openalex-snapshot

A study of dynamic scheduling techniques for multiscalar processors

inferredcites →https://doi.org/10.1109/isca.1998.694770openalex-snapshot

Memory dependence prediction using store sets

inferredcites →https://doi.org/10.1109/isca.2005.46openalex-snapshot

Scalable Load and Store Processing in Latency Tolerant Processors

inferredcites →https://doi.org/10.1109/isca.2005.47openalex-snapshot

Store Buffer Design in First-Level Multibanked Data Caches

inferredcites →https://doi.org/10.1109/isca.2005.48openalex-snapshot

Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization

inferredcites →https://doi.org/10.1109/micro.1997.645812openalex-snapshot

Improving the accuracy and performance of memory communication through renaming

inferredcites →https://doi.org/10.1109/micro.1997.645814openalex-snapshot

Streamlining inter-operation memory communication via data dependence prediction

inferredcites →https://doi.org/10.1109/micro.1998.742783openalex-snapshot

A novel renaming scheme to exploit value temporal locality through physical register reuse and unification

inferredcites →https://doi.org/10.1109/micro.2003.1253244openalex-snapshot

Scalable hardware memory disambiguation for high ILP processors

inferredcites →https://doi.org/10.1109/micro.2003.1253245openalex-snapshot

Reducing design complexity of the load/store queue

inferredcites →https://doi.org/10.1109/micro.2003.1253246openalex-snapshot

Checkpoint processing and recovery: towards scalable large instruction window processors

inferredcites →https://doi.org/10.1109/mm.2004.81openalex-snapshot

Memory ordering: a value-based approach

inferredcites →https://doi.org/10.1109/mm.2004.87openalex-snapshot

Scalable hardware memory disambiguation for high-ILP processors

inferredcites →https://doi.org/10.1145/1028176.1006709openalex-snapshot

Memory Ordering

inferredcites →https://doi.org/10.1145/1080695.1070007openalex-snapshot

Scalable Load and Store Processing in Latency Tolerant Processors

inferredcites →https://doi.org/10.1145/1080695.1070008openalex-snapshot

Store Vulnerability Window (SVW)

inferredcites →https://doi.org/10.1145/1080695.1070009openalex-snapshot

Store Buffer Design in First-Level Multibanked Data Caches

inferredcites →https://doi.org/10.1145/139669.139703openalex-snapshot

The expandable split window paradigm for exploiting fine-grain parallelsim

inferredcites →https://doi.org/10.1145/146628.139703openalex-snapshot

The expandable split window paradigm for exploiting fine-grain parallelism

inferredcites →https://doi.org/10.1145/195473.195534openalex-snapshot

Dynamic memory disambiguation using the memory conflict buffer

inferredcites →https://doi.org/10.1145/223982.224451openalex-snapshot

Multiscalar processors

inferredcites →https://doi.org/10.1145/264107.264189openalex-snapshot

Dynamic speculation and synchronization of data dependences

inferredcites →https://doi.org/10.1145/279358.279378openalex-snapshot

Memory dependence prediction using store sets

inferredcites →https://doi.org/10.1145/319838.319854openalex-snapshot

An architecture for mostly functional languages

inferredcites →https://doi.org/10.1145/357353.357355openalex-snapshot

Implementing atomic actions on decentralized data

inferredcites →https://doi.org/10.5555/266800.266823openalex-snapshot

Streamlining inter-operation memory communication via data dependence prediction

inferredcites →https://doi.org/10.5555/320080.320105openalex-snapshot

Dynamic memory disambiguation in the presence of out-of-order store issuing

inferredcites →https://doi.org/10.5555/956417.956554openalex-snapshot

Checkpoint processing and recovery: towards scalable large instruction window processors

inferredcites →https://doi.org/10.5555/956417.956555openalex-snapshot

Reducing design complexity of the load/store queue

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/s11390-012-1263-7openalex-snapshot

Active Store Window: Enabling Far Store-Load Forwarding with Scalability and Complexity-Efficiency

inferred← citeshttps://doi.org/10.1049/ip-cdt:20050218openalex-snapshot

LSQ: a power efficient and scalable implementation

inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408522openalex-snapshot

Tempranillo: Non-Speculative Early Register Release

inferred← citeshttps://doi.org/10.1109/iccd.2007.4601888openalex-snapshot

A position-insensitive finished store buffer

inferred← citeshttps://doi.org/10.1109/iccd.2012.6378654openalex-snapshot

SOLE: Speculative one-cycle load execution with scalability, high-performance and energy-efficiency

inferred← citeshttps://doi.org/10.1109/icicm63644.2024.10814260openalex-snapshot

Dynamic Path-Sensitive Memory Dependence Prediction

inferred← citeshttps://doi.org/10.1109/isca.2006.36openalex-snapshot

Slackened Memory Dependence Enforcement: Combining Opportunistic Forwarding with Decoupled Verification

inferred← citeshttps://doi.org/10.1109/isca.2008.6openalex-snapshot

Counting Dependence Predictors

inferred← citeshttps://doi.org/10.1109/isca.2018.00029openalex-snapshot

Dynamic Memory Dependence Predication

inferred← citeshttps://doi.org/10.1109/isca59077.2024.00074openalex-snapshot

Compiler-Directed Whole-System Persistence

inferred← citeshttps://doi.org/10.1109/ispass64960.2025.00032openalex-snapshot

COSMOS: An LLC Contention Slowdown Model for Heterogeneous Multi-Core Systems

inferred← citeshttps://doi.org/10.1109/lpe.2006.4271848openalex-snapshot

Substituting Associative Load Queue with Simple Hash Tables in Out-of-Order Microprocessors

inferred← citeshttps://doi.org/10.1109/micro.2006.21openalex-snapshot

DMDC: Delayed Memory Dependence Checking through Age-Based Filtering

inferred← citeshttps://doi.org/10.1109/micro.2006.26openalex-snapshot

Fire-and-Forget: Load/Store Scheduling with No Store Queue at All

inferred← citeshttps://doi.org/10.1109/micro.2006.39openalex-snapshot

NoSQ: Store-Load Communication without a Store Queue

inferred← citeshttps://doi.org/10.1109/mm.2007.17openalex-snapshot

NoSQ: Store-Load Communication without a Store Queue

inferred← citeshttps://doi.org/10.1109/mwscas.2007.4488819openalex-snapshot

Design trade-offs for load/store buffers in embedded processing environments

inferred← citeshttps://doi.org/10.1109/pact.2009.29openalex-snapshot

Zero-Value Caches: Cancelling Loads that Return Zero

inferred← citeshttps://doi.org/10.1109/sp61157.2025.00039openalex-snapshot

Tiktag: Breaking ARM's Memory Tagging Extension with Speculative Execution

inferred← citeshttps://doi.org/10.1109/tc.2008.146openalex-snapshot

Replacing Associative Load Queues: A Timing-Centric Approach

inferred← citeshttps://doi.org/10.1109/tc.2009.57openalex-snapshot

Store Buffer Design for Multibanked Data Caches

inferred← citeshttps://doi.org/10.1145/1150019.1136498openalex-snapshot

Slackened Memory Dependence Enforcement

inferred← citeshttps://doi.org/10.1145/1165573.1165637openalex-snapshot

Substituting associative load queue with simple hash tables in out-of-order microprocessors

inferred← citeshttps://doi.org/10.1145/1250662.1250705openalex-snapshot

Late-binding

inferred← citeshttps://doi.org/10.1145/1273440.1250705openalex-snapshot

Late-binding

inferred← citeshttps://doi.org/10.1145/1366230.1366261openalex-snapshot

A modular 3d processor for flexible product design and technology migration

inferred← citeshttps://doi.org/10.1145/1394608.1382140openalex-snapshot

Counting Dependence Predictors

inferred← citeshttps://doi.org/10.1145/1509084.1509087openalex-snapshot

Zero loads

inferred← citeshttps://doi.org/10.1145/2038698.2038710openalex-snapshot

A unified approach to eliminate memory accesses early

inferred← citeshttps://doi.org/10.1145/3280848openalex-snapshot

Static Prediction of Silent Stores

inferred← citeshttps://doi.org/10.1145/3603619openalex-snapshot

Transient-Execution Attacks: A Computer Architect Perspective

inferred← citeshttps://doi.org/10.5821/dissertation-2117-95043openalex-snapshot

Design of a distributed memory unit for clustered microarchitectures

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