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NoSQ: Store-Load Communication without a Store Queue
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/2.612250openalex-snapshot
Superspeculative microarchitecture for beyond AD 2000
inferredcites →https://doi.org/10.1109/hpca.2006.1598113openalex-snapshot
Store Vectors for Scalable Memory Dependence Prediction and Scheduling
inferredcites →https://doi.org/10.1109/isca.1998.694770openalex-snapshot
Memory dependence prediction using store sets
inferredcites →https://doi.org/10.1109/isca.1999.765938openalex-snapshot
Speculation techniques for improving load related instruction scheduling
inferredcites →https://doi.org/10.1109/isca.2005.43openalex-snapshot
RENO: a rename-based instruction optimizer
inferredcites →https://doi.org/10.1109/isca.2005.46openalex-snapshot
Scalable Load and Store Processing in Latency Tolerant Processors
inferredcites →https://doi.org/10.1109/isca.2005.47openalex-snapshot
Store Buffer Design in First-Level Multibanked Data Caches
inferredcites →https://doi.org/10.1109/isca.2005.48openalex-snapshot
Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization
inferredcites →https://doi.org/10.1109/isca.2006.36openalex-snapshot
Slackened Memory Dependence Enforcement: Combining Opportunistic Forwarding with Decoupled Verification
inferredcites →https://doi.org/10.1109/isscc.1997.585464openalex-snapshot
A 5 ns store barrier cache with dynamic prediction of load/store conflicts in superscalar processors
inferredcites →https://doi.org/10.1109/micro.1997.645812openalex-snapshot
Improving the accuracy and performance of memory communication through renaming
inferredcites →https://doi.org/10.1109/micro.1997.645814openalex-snapshot
Streamlining inter-operation memory communication via data dependence prediction
inferredcites →https://doi.org/10.1109/micro.2003.1253244openalex-snapshot
Scalable hardware memory disambiguation for high ILP processors
inferredcites →https://doi.org/10.1109/micro.2003.1253245openalex-snapshot
Reducing design complexity of the load/store queue
inferredcites →https://doi.org/10.1109/micro.2005.10openalex-snapshot
Address-Indexed Memory Disambiguation and Store-to-Load Forwarding
inferredcites →https://doi.org/10.1109/micro.2005.29openalex-snapshot
Scalable Store-Load Forwarding via Store Queue Index Prediction
inferredcites →https://doi.org/10.1109/micro.2006.26openalex-snapshot
Fire-and-Forget: Load/Store Scheduling with No Store Queue at All
inferredcites →https://doi.org/10.1109/mm.2004.87openalex-snapshot
Scalable hardware memory disambiguation for high-ILP processors
inferredcites →https://doi.org/10.1145/1080695.1070007openalex-snapshot
Scalable Load and Store Processing in Latency Tolerant Processors
inferredcites →https://doi.org/10.1145/1080695.1070008openalex-snapshot
Store Vulnerability Window (SVW)
inferredcites →https://doi.org/10.1145/1080695.1070009openalex-snapshot
Store Buffer Design in First-Level Multibanked Data Caches
inferredcites →https://doi.org/10.1145/1150019.1136498openalex-snapshot
Slackened Memory Dependence Enforcement
inferredcites →https://doi.org/10.1145/279358.279378openalex-snapshot
Memory dependence prediction using store sets
inferredcites →https://doi.org/10.1145/300979.300983openalex-snapshot
Speculation techniques for improving load related instruction scheduling
inferredcites →https://doi.org/10.1145/377792.377850openalex-snapshot
Load and store reuse using register file contents
inferredcites →https://doi.org/10.1147/rd.502.0287openalex-snapshot
Decomposing the load-store queue by function for power reduction and scalability
inferredcites →https://doi.org/10.5555/266800.266823openalex-snapshot
Streamlining inter-operation memory communication via data dependence prediction
inferredcites →https://doi.org/10.5555/956417.956555openalex-snapshot
Reducing design complexity of the load/store queue
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11390-012-1263-7openalex-snapshot
Active Store Window: Enabling Far Store-Load Forwarding with Scalability and Complexity-Efficiency
inferred← citeshttps://doi.org/10.1109/fpt.2013.6718409openalex-snapshot
Efficient methods for out-of-order load/store execution for high-performance soft processors
inferred← citeshttps://doi.org/10.1109/hpca.2008.4658634openalex-snapshot
PEEP: Exploiting predictability of memory dependences in SMT processors
inferred← citeshttps://doi.org/10.1109/hpca.2009.4798280openalex-snapshot
Criticality-based optimizations for efficient load processing
inferred← citeshttps://doi.org/10.1109/hpca.2012.6169033openalex-snapshot
Flexible register management using reference counting
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446105openalex-snapshot
Cost effective physical register sharing
inferred← citeshttps://doi.org/10.1109/hpca.2018.00066openalex-snapshot
NACHOS: Software-Driven Hardware-Assisted Memory Disambiguation for Accelerators
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00039openalex-snapshot
CASINO Core Microarchitecture: Generating Out-of-Order Schedules Using Cascaded In-Order Scheduling Windows
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00045openalex-snapshot
Effective Context-Sensitive Memory Dependence Prediction
inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00016openalex-snapshot
Mascot: Predicting Memory Dependencies and Opportunities for Speculative Memory Bypassing
inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408465openalex-snapshot
SSBleed: Non-Speculative Side-Channel Attacks via Speculative Store Bypass on Armv9 CPUs
inferred← citeshttps://doi.org/10.1109/iccd.2007.4601888openalex-snapshot
A position-insensitive finished store buffer
inferred← citeshttps://doi.org/10.1109/iccd.2012.6378654openalex-snapshot
SOLE: Speculative one-cycle load execution with scalability, high-performance and energy-efficiency
inferred← citeshttps://doi.org/10.1109/icicm63644.2024.10814260openalex-snapshot
Dynamic Path-Sensitive Memory Dependence Prediction
inferred← citeshttps://doi.org/10.1109/isca.2008.10openalex-snapshot
A Two-Level Load/Store Queue Based on Execution Locality
inferred← citeshttps://doi.org/10.1109/isca.2014.6853196openalex-snapshot
Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures
inferred← citeshttps://doi.org/10.1109/isca.2018.00029openalex-snapshot
Dynamic Memory Dependence Predication
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00018openalex-snapshot
Focused Value Prediction: Concepts, techniques and implementations presented in this paper are subject matter of pending patent applications, which have been filed by Intel Corporation
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00127openalex-snapshot
SSBench: Automated Characterization of Memory Dependence Predictors on Modern CPUs
inferred← citeshttps://doi.org/10.1109/l-ca.2007.15openalex-snapshot
Physical register reference counting
inferred← citeshttps://doi.org/10.1109/lca.2016.2628379openalex-snapshot
Storage-Free Memory Dependency Prediction
inferred← citeshttps://doi.org/10.1109/micro.2006.26openalex-snapshot
Fire-and-Forget: Load/Store Scheduling with No Store Queue at All
inferred← citeshttps://doi.org/10.1109/micro.2016.7783707openalex-snapshot
Register sharing for equality prediction
inferred← citeshttps://doi.org/10.1109/mm.2007.17openalex-snapshot
NoSQ: Store-Load Communication without a Store Queue
inferred← citeshttps://doi.org/10.1109/pact.2007.10openalex-snapshot
A Scalable Low Power Store Queue for Large InstructionWindow Processors
inferred← citeshttps://doi.org/10.1109/pact.2009.29openalex-snapshot
Zero-Value Caches: Cancelling Loads that Return Zero
inferred← citeshttps://doi.org/10.1109/tc.2008.146openalex-snapshot
Replacing Associative Load Queues: A Timing-Centric Approach
inferred← citeshttps://doi.org/10.1109/tc.2010.131openalex-snapshot
Macro Data Load: An Efficient Mechanism for Enhancing Loaded Data Reuse
inferred← citeshttps://doi.org/10.1109/tvlsi.2010.2064185openalex-snapshot
Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management
inferred← citeshttps://doi.org/10.1145/1250662.1250696openalex-snapshot
Mechanisms for store-wait-free multiprocessors
inferred← citeshttps://doi.org/10.1145/1273440.1250696openalex-snapshot
Mechanisms for store-wait-free multiprocessors
inferred← citeshttps://doi.org/10.1145/1366230.1366261openalex-snapshot
A modular 3d processor for flexible product design and technology migration
inferred← citeshttps://doi.org/10.1145/1394608.1382140openalex-snapshot
Counting Dependence Predictors
inferred← citeshttps://doi.org/10.1145/1394608.1382171openalex-snapshot
A Two-Level Load/Store Queue Based on Execution Locality
inferred← citeshttps://doi.org/10.1145/1555754.1555786openalex-snapshot
Decoupled store completion/silent deterministic replay
inferred← citeshttps://doi.org/10.1145/1555815.1555786openalex-snapshot
Decoupled store completion/silent deterministic replay
inferred← citeshttps://doi.org/10.1145/1596510.1596514openalex-snapshot
Design and optimization of the store vectors memory dependence predictor
inferred← citeshttps://doi.org/10.1145/2038698.2038710openalex-snapshot
A unified approach to eliminate memory accesses early
inferred← citeshttps://doi.org/10.1145/3243176.3243208openalex-snapshot
Cost effective speculation with the omnipredictor
inferred← citeshttps://doi.org/10.1145/3613424.3614272openalex-snapshot
Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors
inferred← citeshttps://doi.org/10.1145/3658644.3690214openalex-snapshot
SemPat: From Hyperproperties to Attack Patterns for Scalable Analysis of Microarchitectural Security
inferred← citeshttps://doi.org/10.1145/3725843.3762248openalex-snapshot
Multi-Stream Squash Reuse for Control-Independent Processors
inferred← citeshttps://doi.org/10.1587/transele.e98.c.580openalex-snapshot
Address Order Violation Detection with Parallel Counting Bloom Filters
inferred← citeshttps://doi.org/10.2200/s00677ed1v01y201511cac034openalex-snapshot
Research Infrastructures for Hardware Accelerators
inferred← citeshttps://doi.org/10.36548/jsws.2021.4.001openalex-snapshot
Design of Low Power Cam Memory Cell for the Next Generation Network Processors
inferred← citeshttps://doi.org/10.48550/arxiv.1606.01607openalex-snapshot
CG-OoO: Energy-Efficient Coarse-Grain Out-of-Order Execution
inferred← citeshttps://doi.org/10.5555/3195638.3195684openalex-snapshot
Poisonivy: safe speculation for secure memory
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