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Scalable Store-Load Forwarding via Store Queue Index Prediction

https://doi.org/10.1109/micro.2005.29
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/12.509907openalex-snapshot
ARB: a hardware mechanism for dynamic reordering of memory references
inferredcites →https://doi.org/10.1109/40.755465openalex-snapshot
The Alpha 21264 microprocessor
inferredcites →https://doi.org/10.1109/hpca.2000.824359openalex-snapshot
Memory dependence speculation tradeoffs in centralized, continuous-window superscalar processors
inferredcites →https://doi.org/10.1109/hpca.2004.10011openalex-snapshot
Understanding Scheduling Replay Schemes
inferredcites →https://doi.org/10.1109/isca.1998.694770openalex-snapshot
Memory dependence prediction using store sets
inferredcites →https://doi.org/10.1109/isca.1999.765938openalex-snapshot
Speculation techniques for improving load related instruction scheduling
inferredcites →https://doi.org/10.1109/isca.2005.46openalex-snapshot
Scalable Load and Store Processing in Latency Tolerant Processors
inferredcites →https://doi.org/10.1109/isca.2005.47openalex-snapshot
Store Buffer Design in First-Level Multibanked Data Caches
inferredcites →https://doi.org/10.1109/isca.2005.48openalex-snapshot
Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization
inferredcites →https://doi.org/10.1109/micro.1997.645812openalex-snapshot
Improving the accuracy and performance of memory communication through renaming
inferredcites →https://doi.org/10.1109/micro.1997.645814openalex-snapshot
Streamlining inter-operation memory communication via data dependence prediction
inferredcites →https://doi.org/10.1109/micro.2003.1253244openalex-snapshot
Scalable hardware memory disambiguation for high ILP processors
inferredcites →https://doi.org/10.1109/micro.2003.1253245openalex-snapshot
Reducing design complexity of the load/store queue
inferredcites →https://doi.org/10.1109/mm.2004.71openalex-snapshot
Continual flow pipelines: achieving resource-efficient latency tolerance
inferredcites →https://doi.org/10.1109/mm.2004.87openalex-snapshot
Scalable hardware memory disambiguation for high-ILP processors
inferredcites →https://doi.org/10.1145/1024393.1024407openalex-snapshot
Continual flow pipelines
inferredcites →https://doi.org/10.1145/1028176.1006709openalex-snapshot
Memory Ordering
inferredcites →https://doi.org/10.1145/1080695.1070007openalex-snapshot
Scalable Load and Store Processing in Latency Tolerant Processors
inferredcites →https://doi.org/10.1145/1080695.1070008openalex-snapshot
Store Vulnerability Window (SVW)
inferredcites →https://doi.org/10.1145/1080695.1070009openalex-snapshot
Store Buffer Design in First-Level Multibanked Data Caches
inferredcites →https://doi.org/10.1145/264107.264189openalex-snapshot
Dynamic speculation and synchronization of data dependences
inferredcites →https://doi.org/10.1145/279358.279378openalex-snapshot
Memory dependence prediction using store sets
inferredcites →https://doi.org/10.1145/300979.300983openalex-snapshot
Speculation techniques for improving load related instruction scheduling
inferredcites →https://doi.org/10.1147/rd.502.0287openalex-snapshot
Decomposing the load-store queue by function for power reduction and scalability
inferredcites →https://doi.org/10.5555/266800.266823openalex-snapshot
Streamlining inter-operation memory communication via data dependence prediction
inferredcites →https://doi.org/10.5555/320080.320105openalex-snapshot
Dynamic memory disambiguation in the presence of out-of-order store issuing
inferredcites →https://doi.org/10.5555/956417.956555openalex-snapshot
Reducing design complexity of the load/store queue

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-642-17752-1_12openalex-snapshot
L1 Data Cache Power Reduction Using a Forwarding Predictor
inferred← citeshttps://doi.org/10.1007/s11390-012-1263-7openalex-snapshot
Active Store Window: Enabling Far Store-Load Forwarding with Scalability and Complexity-Efficiency
inferred← citeshttps://doi.org/10.1016/j.sysarc.2008.09.005openalex-snapshot
Using age registers for a simple load–store queue filtering
inferred← citeshttps://doi.org/10.1016/j.sysarc.2009.10.001openalex-snapshot
On reducing load/store latencies of cache accesses
inferred← citeshttps://doi.org/10.1109/fpt.2013.6718409openalex-snapshot
Efficient methods for out-of-order load/store execution for high-performance soft processors
inferred← citeshttps://doi.org/10.1109/hpca.2008.4658634openalex-snapshot
PEEP: Exploiting predictability of memory dependences in SMT processors
inferred← citeshttps://doi.org/10.1109/hpca.2010.5416634openalex-snapshot
BOLT: Energy-efficient Out-of-Order Latency-Tolerant execution
inferred← citeshttps://doi.org/10.1109/hpca.2018.00066openalex-snapshot
NACHOS: Software-Driven Hardware-Assisted Memory Disambiguation for Accelerators
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00039openalex-snapshot
CASINO Core Microarchitecture: Generating Out-of-Order Schedules Using Cascaded In-Order Scheduling Windows
inferred← citeshttps://doi.org/10.1109/iccd.2007.4601888openalex-snapshot
A position-insensitive finished store buffer
inferred← citeshttps://doi.org/10.1109/iccd.2012.6378654openalex-snapshot
SOLE: Speculative one-cycle load execution with scalability, high-performance and energy-efficiency
inferred← citeshttps://doi.org/10.1109/isca.2006.36openalex-snapshot
Slackened Memory Dependence Enforcement: Combining Opportunistic Forwarding with Decoupled Verification
inferred← citeshttps://doi.org/10.1109/isca.2008.6openalex-snapshot
Counting Dependence Predictors
inferred← citeshttps://doi.org/10.1109/isca.2018.00029openalex-snapshot
Dynamic Memory Dependence Predication
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00074openalex-snapshot
Compiler-Directed Whole-System Persistence
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00127openalex-snapshot
SSBench: Automated Characterization of Memory Dependence Predictors on Modern CPUs
inferred← citeshttps://doi.org/10.1109/lpe.2006.4271825openalex-snapshot
Reducing Cache Traffic and Energy with Macro Data Load
inferred← citeshttps://doi.org/10.1109/lpe.2006.4271848openalex-snapshot
Substituting Associative Load Queue with Simple Hash Tables in Out-of-Order Microprocessors
inferred← citeshttps://doi.org/10.1109/micro.2006.21openalex-snapshot
DMDC: Delayed Memory Dependence Checking through Age-Based Filtering
inferred← citeshttps://doi.org/10.1109/micro.2006.26openalex-snapshot
Fire-and-Forget: Load/Store Scheduling with No Store Queue at All
inferred← citeshttps://doi.org/10.1109/micro.2006.39openalex-snapshot
NoSQ: Store-Load Communication without a Store Queue
inferred← citeshttps://doi.org/10.1109/micro.2014.60openalex-snapshot
Short-Circuiting Memory Traffic in Handheld Platforms
inferred← citeshttps://doi.org/10.1109/micro.2016.7783741openalex-snapshot
PoisonIvy: Safe speculation for secure memory
inferred← citeshttps://doi.org/10.1109/mm.2007.17openalex-snapshot
NoSQ: Store-Load Communication without a Store Queue
inferred← citeshttps://doi.org/10.1109/pact.2007.10openalex-snapshot
A Scalable Low Power Store Queue for Large InstructionWindow Processors
inferred← citeshttps://doi.org/10.1109/tc.2008.146openalex-snapshot
Replacing Associative Load Queues: A Timing-Centric Approach
inferred← citeshttps://doi.org/10.1109/tc.2009.57openalex-snapshot
Store Buffer Design for Multibanked Data Caches
inferred← citeshttps://doi.org/10.1109/tc.2010.131openalex-snapshot
Macro Data Load: An Efficient Mechanism for Enhancing Loaded Data Reuse
inferred← citeshttps://doi.org/10.1145/1150019.1136498openalex-snapshot
Slackened Memory Dependence Enforcement
inferred← citeshttps://doi.org/10.1145/1165573.1165608openalex-snapshot
Reducing cache traffic and energy with macro data load
inferred← citeshttps://doi.org/10.1145/1165573.1165637openalex-snapshot
Substituting associative load queue with simple hash tables in out-of-order microprocessors
inferred← citeshttps://doi.org/10.1145/1250662.1250705openalex-snapshot
Late-binding
inferred← citeshttps://doi.org/10.1145/1250662.1250716openalex-snapshot
Ginger
inferred← citeshttps://doi.org/10.1145/1273440.1250705openalex-snapshot
Late-binding
inferred← citeshttps://doi.org/10.1145/1273440.1250716openalex-snapshot
Ginger
inferred← citeshttps://doi.org/10.1145/1366230.1366261openalex-snapshot
A modular 3d processor for flexible product design and technology migration
inferred← citeshttps://doi.org/10.1145/1394608.1382140openalex-snapshot
Counting Dependence Predictors
inferred← citeshttps://doi.org/10.1145/1509084.1509087openalex-snapshot
Zero loads
inferred← citeshttps://doi.org/10.1145/1555754.1555786openalex-snapshot
Decoupled store completion/silent deterministic replay
inferred← citeshttps://doi.org/10.1145/1555815.1555786openalex-snapshot
Decoupled store completion/silent deterministic replay
inferred← citeshttps://doi.org/10.1145/1596510.1596514openalex-snapshot
Design and optimization of the store vectors memory dependence predictor
inferred← citeshttps://doi.org/10.1145/1880043.1880046openalex-snapshot
Federation
inferred← citeshttps://doi.org/10.1145/2597917.2597940openalex-snapshot
SAMO
inferred← citeshttps://doi.org/10.1145/2656106.2656109openalex-snapshot
A low-cost memory interface for high-throughput accelerators
inferred← citeshttps://doi.org/10.1145/2800787openalex-snapshot
Revisiting Clustered Microarchitecture for Future Superscalar Cores
inferred← citeshttps://doi.org/10.1145/3178372.3179529openalex-snapshot
Polyhedral expression propagation
inferred← citeshttps://doi.org/10.1145/3307650.3322269openalex-snapshot
Filter caching for free
inferred← citeshttps://doi.org/10.1145/3428215openalex-snapshot
Exposing cache timing side-channel leaks through out-of-order symbolic execution
inferred← citeshttps://doi.org/10.1145/3466752.3480042openalex-snapshot
Turnpike: Lightweight Soft Error Resilience for In-Order Cores
inferred← citeshttps://doi.org/10.1587/transele.e98.c.580openalex-snapshot
Address Order Violation Detection with Parallel Counting Bloom Filters
inferred← citeshttps://doi.org/10.1587/transinf.2015edp7325openalex-snapshot
Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control
inferred← citeshttps://doi.org/10.35537/10915/18411openalex-snapshot
Computer Science & Technology Series
inferred← citeshttps://doi.org/10.35537/10915/48825openalex-snapshot
Computer Science & Technology Series
inferred← citeshttps://doi.org/10.5555/3195638.3195684openalex-snapshot
Poisonivy: safe speculation for secure memory
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95043openalex-snapshot
Design of a distributed memory unit for clustered microarchitectures
inferred← citeshttps://doi.org/10.70675/9cf1b1cdz4744z49b5z9bc2zdd9658d77063openalex-snapshot
Revisiting Wide Superscalar Microarchitecture
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