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A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1006/jpdc.2000.1669openalex-snapshot
Evaluation of Crossbar Architectures for Deadlock Recovery Routers
inferredcites →https://doi.org/10.1007/10704826_5openalex-snapshot
Performance Evaluation of the Multimedia Router with MPEG-2 Video Traffic
inferredcites →https://doi.org/10.1007/978-1-4020-6488-3_12openalex-snapshot
xpipesCompiler: A Tool for Instantiating Application-Specific Networks on Chip
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/71.940747openalex-snapshot
SimpleFit: a framework for analyzing design trade-offs in Raw architectures
inferredcites →https://doi.org/10.1109/aspdac.2003.1195022openalex-snapshot
Energy-aware mapping for tile-based NoC architectures under performance constraints
inferredcites →https://doi.org/10.1109/date.2005.40openalex-snapshot
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
inferredcites →https://doi.org/10.1109/hpca.1996.501186openalex-snapshot
Fault-tolerance with multimodule routers
inferredcites →https://doi.org/10.1109/hpca.2001.903268openalex-snapshot
A delay model and speculative architecture for pipelined routers
inferredcites →https://doi.org/10.1109/isca.2004.1310774openalex-snapshot
Low-latency virtual-channel routers for on-chip networks
inferredcites →https://doi.org/10.1109/isca.2005.34openalex-snapshot
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
inferredcites →https://doi.org/10.1109/isca.2005.35openalex-snapshot
Microarchitecture of a High-Radix Router
inferredcites →https://doi.org/10.1109/isvlsi.2003.1183347openalex-snapshot
Networks-on-chip: the quest for on-chip fault-tolerant communication
inferredcites →https://doi.org/10.1109/mdt.2005.111openalex-snapshot
Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research
inferredcites →https://doi.org/10.1109/mdt.2005.99openalex-snapshot
Æthereal Network on Chip:Concepts, Architectures, and Implementations
inferredcites →https://doi.org/10.1109/micro.2003.1253187openalex-snapshot
Power-driven design of router microarchitectures in on-chip networks
inferredcites →https://doi.org/10.1109/micro.2004.35openalex-snapshot
Thermal Modeling, Characterization and Management of On-Chip Networks
inferredcites →https://doi.org/10.1109/mm.2002.997877openalex-snapshot
The Raw microprocessor: a computational fabric for software circuits and general-purpose programs
inferredcites →https://doi.org/10.1109/tc.2005.134openalex-snapshot
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
inferredcites →https://doi.org/10.1109/tpds.2002.1003858openalex-snapshot
HiPER: a compact narrow channel router with hop-by-hop error correction
inferredcites →https://doi.org/10.1145/1023833.1023849openalex-snapshot
High-level power analysis for on-chip networks
inferredcites →https://doi.org/10.1145/1065579.1065726openalex-snapshot
A low latency router supporting adaptivity for on-chip interconnects
inferredcites →https://doi.org/10.1145/277851.277897openalex-snapshot
Generating representative Web workloads for network and server performance evaluation
inferredcites →https://doi.org/10.1145/859618.859667openalex-snapshot
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1109/access.2023.3235276openalex-snapshot
A Top-Down Modeling Approach for Networks-on-Chip Components Design: A Switch as Case Study
inferred← citeshttps://doi.org/10.1109/aismot.2011.6159381openalex-snapshot
Low-cost router microarchitecture based on dimension-switch for fault-tolerance in 2D-Mesh NoC
inferred← citeshttps://doi.org/10.1109/dac.2018.8465889openalex-snapshot
Packet Pump: Overcoming Network Bottleneck in On-Chip Interconnects for GPGPUs
inferred← citeshttps://doi.org/10.1109/dsd.2011.54openalex-snapshot
Design of Fault Tolerant Network Interfaces for NoCs
inferred← citeshttps://doi.org/10.1109/hpca.2009.4798274openalex-snapshot
Prediction router: Yet another low latency on-chip router architecture
inferred← citeshttps://doi.org/10.1109/hpca.2010.5416639openalex-snapshot
Towards scalable, energy-efficient, bus-based on-chip networks
inferred← citeshttps://doi.org/10.1109/hpcc.2012.47openalex-snapshot
Express Router Microarchitecture for Triplet-based Hierarchical Interconnection Network
inferred← citeshttps://doi.org/10.1109/ic4.2015.7375574openalex-snapshot
A fine grained position for modular core on NoC
inferred← citeshttps://doi.org/10.1109/icsict.2008.4734937openalex-snapshot
Design and analysis of on-chip router
inferred← citeshttps://doi.org/10.1109/ipdpsw.2012.119openalex-snapshot
Energy-Efficient and Fault-Tolerant Unified Buffer and Bufferless Crossbar Architecture for NoCs
inferred← citeshttps://doi.org/10.1109/isca.2008.13openalex-snapshot
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
inferred← citeshttps://doi.org/10.1109/isqed.2011.5770788openalex-snapshot
ERAVC: Enhanced reliability aware NoC router
inferred← citeshttps://doi.org/10.1109/isvlsi.2014.70openalex-snapshot
Towards an Effective Utilization of Partially Defected Interconnections in 2D Mesh NoCs
inferred← citeshttps://doi.org/10.1109/itng.2012.117openalex-snapshot
Loopback Virtual Channel Router Architecture for Network on Chip
inferred← citeshttps://doi.org/10.1109/iwia.2007.8openalex-snapshot
Impact of Predictive Switching in 2-D Torus Networks
inferred← citeshttps://doi.org/10.1109/nanonet.2006.346214openalex-snapshot
A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects
inferred← citeshttps://doi.org/10.1109/nocs.2007.26openalex-snapshot
Implications of Rent's Rule for NoC Design and Its Fault-Tolerance
inferred← citeshttps://doi.org/10.1109/nocs.2010.17openalex-snapshot
Design of a High-Throughput Distributed Shared-Buffer NoC Router
inferred← citeshttps://doi.org/10.1109/prime.2015.7251084openalex-snapshot
Communication energy constrained spare core on NoC
inferred← citeshttps://doi.org/10.1109/tc.2011.17openalex-snapshot
Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors
inferred← citeshttps://doi.org/10.1109/tc.2015.2401013openalex-snapshot
Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures
inferred← citeshttps://doi.org/10.1109/tcad.2011.2110550openalex-snapshot
Extending the Effective Throughput of NoCs With Distributed Shared-Buffer Routers
inferred← citeshttps://doi.org/10.1109/tvlsi.2008.2000994openalex-snapshot
Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks
inferred← citeshttps://doi.org/10.1109/tvlsi.2012.2227283openalex-snapshot
Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips
inferred← citeshttps://doi.org/10.1145/1250662.1250680openalex-snapshot
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
inferred← citeshttps://doi.org/10.1145/1273440.1250680openalex-snapshot
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
inferred← citeshttps://doi.org/10.1145/1323548.1323561openalex-snapshot
Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture
inferred← citeshttps://doi.org/10.1145/1531542.1531658openalex-snapshot
Reliability aware NoC router architecture using input channel buffer sharing
inferred← citeshttps://doi.org/10.1145/1669112.1669145openalex-snapshot
Low-cost router microarchitecture for on-chip networks
inferred← citeshttps://doi.org/10.1145/2380445.2380461openalex-snapshot
A novel NoC-based design for fault-tolerance of last-level caches in CMPs
inferred← citeshttps://doi.org/10.1145/2485984.2485993openalex-snapshot
Addressing network-on-chip router transient errors with inherent information redundancy
inferred← citeshttps://doi.org/10.1145/2509420.2512433openalex-snapshot
Scalable high-radix router microarchitecture using a network switch organization
inferred← citeshttps://doi.org/10.1145/2522968.2522976openalex-snapshot
Methods for fault tolerance in networks-on-chip
inferred← citeshttps://doi.org/10.1145/2567939openalex-snapshot
NoC-based fault-tolerant cache design in chip multiprocessors
inferred← citeshttps://doi.org/10.1145/2742349openalex-snapshot
Simple Virtual Channel Allocation for High-Throughput and High-Frequency On-Chip Routers
inferred← citeshttps://doi.org/10.1145/3529106openalex-snapshot
A Segmented Adaptive Router for Near Energy-Proportional Networks-on-Chip
inferred← citeshttps://doi.org/10.2200/s00365ed1v01y201105cac017openalex-snapshot
Multi-Core Cache Hierarchies
inferred← citeshttps://doi.org/10.2200/s00772ed1v01y201704cac040openalex-snapshot
On-Chip Networks, Second Edition
inferred← citeshttps://doi.org/10.2991/icmt-13.2013.158openalex-snapshot
Router Design and Implementation for a Polymorphic Multimedia Processor
inferred← citeshttps://doi.org/10.32920/ryerson.14656014openalex-snapshot
Application mapping and NoC configuration using hybrid particle swarm optimization
inferred← citeshttps://doi.org/10.32920/ryerson.14656014.v1openalex-snapshot
Application mapping and NoC configuration using hybrid particle swarm optimization
inferred← citeshttps://doi.org/10.4108/eai.28-8-2017.153307openalex-snapshot
A Virtual Channel Allocation Algorithm for NoC
inferred← citeshttps://doi.org/10.5120/ijca2017914875openalex-snapshot
A Review of the Design Challenges for the 3-D on Chip Network Paradigms
inferred← citeshttps://doi.org/10.5821/dissertation-2117-113292openalex-snapshot
Contribution to the architecture and implementation of Bi-NoC routers for multi-synchronous GALS systems
inferred← citeshttps://doi.org/10.5821/dissertation-2117-93339openalex-snapshot
Affordable kilo-instruction processors
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