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Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-44520-x_137openalex-snapshot
BitValue Inference: Detecting and Exploiting Narrow Bitwidth Computations
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The Mips R10000 superscalar microprocessor
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Software-controlled operand-gating
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Dynamically exploiting narrow width operands to improve processor power and performance
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Dynamic cluster assignment mechanisms
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In-line interrupt handling for software-managed TLBs
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Energy efficient asymmetrically ported register files
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Defining wakeup width for efficient dynamic scheduling
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Increasing processor performance through early register release
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Hardware schemes for early register release
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Use-based register caching with decoupled indexing
inferredcites →https://doi.org/10.1109/ispass.2004.1291358openalex-snapshot
Dynamically reducing pressure on the physical register file through simple register sharing
inferredcites →https://doi.org/10.1109/micro.1992.697025openalex-snapshot
Register Traffic Analysis For Streamlining Inter-operation Communication In Fine-grain Parallel Processors
inferredcites →https://doi.org/10.1109/micro.1993.282742openalex-snapshot
The 16-fold way: a microparallel taxonomy
inferredcites →https://doi.org/10.1109/micro.1997.645804openalex-snapshot
Exploiting dead value information
inferredcites →https://doi.org/10.1109/micro.1997.645806openalex-snapshot
The multicluster architecture: reducing cycle time through partitioning
inferredcites →https://doi.org/10.1109/micro.1998.742783openalex-snapshot
A novel renaming scheme to exploit value temporal locality through physical register reuse and unification
inferredcites →https://doi.org/10.1109/micro.1999.809456openalex-snapshot
Delaying physical register allocation through virtual-physical registers
inferredcites →https://doi.org/10.1109/micro.2000.898069openalex-snapshot
Very low power pipelines using significance compression
inferredcites →https://doi.org/10.1109/micro.2001.991122openalex-snapshot
Reducing the complexity of the register file in dynamic superscalar processors
inferredcites →https://doi.org/10.1109/micro.2002.1176234openalex-snapshot
Cherry: Checkpointed early resource recycling in out-of-order microprocessors
inferredcites →https://doi.org/10.1109/micro.2002.1176248openalex-snapshot
Reducing register ports for higher speed and lower energy
inferredcites →https://doi.org/10.1109/micro.2002.1176266openalex-snapshot
Exploiting data-width locality to increase superscalar execution bandwidth
inferredcites →https://doi.org/10.1109/micro.2003.1253201openalex-snapshot
Exploiting value locality in physical register files
inferredcites →https://doi.org/10.1109/pact.1996.552666openalex-snapshot
A scalable register file architecture for dynamically scheduled processors
inferredcites →https://doi.org/10.1145/1028176.1006724openalex-snapshot
Use-Based Register Caching with Decoupled Indexing
inferredcites →https://doi.org/10.1145/144965.145818openalex-snapshot
Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors
inferredcites →https://doi.org/10.1145/207110.207117openalex-snapshot
Accurate static branch prediction by value range propagation
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The SimpleScalar tool set, version 2.0
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Table size reduction for data value predictors by exploiting narrow width values
inferredcites →https://doi.org/10.1145/339647.339708openalex-snapshot
Multiple-banked register file architectures
inferredcites →https://doi.org/10.1145/342001.339708openalex-snapshot
Multiple-banked register file architectures
inferredcites →https://doi.org/10.1145/349299.349317openalex-snapshot
Bidwidth analysis with application to silicon compilation
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Dynamic zero compression for cache energy reduction
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inferredcites →https://doi.org/10.1145/782814.782839openalex-snapshot
Reducing register ports using delayed write-back queues and operand pre-fetch
inferredcites →https://doi.org/10.1145/782837.782839openalex-snapshot
Reducing register ports using delayed write-back queues and operand pre-fetch
inferredcites →https://doi.org/10.5555/255235.255288openalex-snapshot
Register renaming and dynamic speculation: an alternative approach
inferredcites →https://doi.org/10.5555/266800.266813openalex-snapshot
Exploiting dead value information
inferredcites →https://doi.org/10.5555/320080.320108openalex-snapshot
Delaying physical register allocation through virtual-physical registers
inferredcites →https://doi.org/10.5555/563998.564029openalex-snapshot
Reducing the complexity of the register file in dynamic superscalar processors
inferredcites →https://doi.org/10.5555/774861.774880openalex-snapshot
Reducing register ports for higher speed and lower energy
inferredcites →https://doi.org/10.5555/774861.774903openalex-snapshot
Exploiting data-width locality to increase superscalar execution bandwidth
inferredcites →https://doi.org/10.5555/956417.956561openalex-snapshot
Exploiting value locality in physical register files
inferredcites →https://doi.org/10.5555/977395.977647openalex-snapshot
Software-controlled operand-gating
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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A survey of techniques for designing and managing CPU register file
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