On the public citation graph

Reducing register ports using delayed write-back queues and operand pre-fetch

https://doi.org/10.1145/782837.782839
0 signed · 28 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1016/j.micpro.2006.08.001openalex-snapshot
Register port complexity reduction in wide-issue processors with selective instruction execution
inferred← citeshttps://doi.org/10.1016/j.micpro.2006.08.004openalex-snapshot
Compacting register file via 2-level renaming and bit-partitioning
inferred← citeshttps://doi.org/10.1023/b:ijpp.0000004510.66751.2eopenalex-snapshot
Power-Aware Compilation for Register File Energy Reduction
inferred← citeshttps://doi.org/10.1109/cahpc.2005.18openalex-snapshot
Chained In-Order/Out-of-Order DoubleCore Architecture
inferred← citeshttps://doi.org/10.1109/icasic.2005.1611275openalex-snapshot
Duplicated Register File Design for Embedded Simultaneous Multithreading Microprocessor
inferred← citeshttps://doi.org/10.1109/iccd.2003.1240920openalex-snapshot
Distributed reorder buffer schemes for low power
inferred← citeshttps://doi.org/10.1109/iccd.2015.7357134openalex-snapshot
A low power buffer-aided vector register file for LTE baseband signal processing
inferred← citeshttps://doi.org/10.1109/icpp.2006.20openalex-snapshot
Address-Value Decoupling for Early Register Deallocation
inferred← citeshttps://doi.org/10.1109/icsamos.2010.5642055openalex-snapshot
Energy-aware design space exploration of registerfile for extensible processors
inferred← citeshttps://doi.org/10.1109/isca.2004.1310784openalex-snapshot
A content aware integer register file organization
inferred← citeshttps://doi.org/10.1109/islped.2015.7273490openalex-snapshot
Bank stealing for conflict mitigation in GPGPU Register File
inferred← citeshttps://doi.org/10.1109/isvlsi.2007.62openalex-snapshot
Investigating Simple Low Latency Reliable Multiported Register Files
inferred← citeshttps://doi.org/10.1109/itng.2006.73openalex-snapshot
Instruction Format Based Selective Execution for Register Port Complexity Reduction in High-Performance Processors
inferred← citeshttps://doi.org/10.1109/lpe.2003.1231868openalex-snapshot
Reducing reorder buffer complexity through selective operand caching
inferred← citeshttps://doi.org/10.1109/lpe.2003.1231931openalex-snapshot
The microarchitecture of a low power register file
inferred← citeshttps://doi.org/10.1109/lpe.2006.4271804openalex-snapshot
Selective Writeback: Exploiting Transient Values for Energy-Efficiency and Performance
inferred← citeshttps://doi.org/10.1109/micro.2004.29openalex-snapshot
Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure
inferred← citeshttps://doi.org/10.1109/micro.2004.8openalex-snapshot
Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy
inferred← citeshttps://doi.org/10.1109/pact.2003.1238021openalex-snapshot
Reducing datapath energy through the isolation of short-lived operands
inferred← citeshttps://doi.org/10.1109/sbac-pad.2007.35openalex-snapshot
Register File Energy Optimization for Snooping Based Clustered VLIW Architectures
inferred← citeshttps://doi.org/10.1109/tc.2004.11openalex-snapshot
Isolating short-lived operands for energy reduction
inferred← citeshttps://doi.org/10.1109/tc.2005.88openalex-snapshot
A Speculative Control Scheme for an Energy-Efficient Banked Register File
inferred← citeshttps://doi.org/10.1109/tc.2006.154openalex-snapshot
Throttling-Based Resource Management in High Performance Multithreaded Architectures
inferred← citeshttps://doi.org/10.1109/tc.2007.70785openalex-snapshot
Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption
inferred← citeshttps://doi.org/10.1109/tcad.2008.923254openalex-snapshot
Register File Power Reduction Using Bypass Sensitive Compiler
inferred← citeshttps://doi.org/10.1109/tpds.2007.70742openalex-snapshot
Operand-Load-Based Split Pipeline Architecture for High Clock Rate and Commensurable IPC
inferred← citeshttps://doi.org/10.1109/tvlsi.2008.2000243openalex-snapshot
Selective Writeback: Reducing Register File Pressure and Energy Consumption
inferred← citeshttps://doi.org/10.1109/tvlsi.2016.2584623openalex-snapshot
Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.