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Reducing register ports using delayed write-back queues and operand pre-fetch

https://doi.org/10.1145/782814.782839
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/hpca.1996.501172openalex-snapshot
Register file design considerations in dynamically scheduled processors
inferredcites →https://doi.org/10.1109/hpca.1998.650557openalex-snapshot
Virtual-physical registers
inferredcites →https://doi.org/10.1109/hpca.2002.995719openalex-snapshot
Loose loops sink chips
inferredcites →https://doi.org/10.1109/isscc.2002.992247openalex-snapshot
Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading
inferredcites →https://doi.org/10.1145/339647.339708openalex-snapshot
Multiple-banked register file architectures
inferredcites →https://doi.org/10.1145/360128.360143openalex-snapshot
Two-level hierarchical register file organization for VLIW processors
inferredcites →https://doi.org/10.1145/545214.545221openalex-snapshot
Efficient dynamic scheduling through tag elimination
inferredcites →https://doi.org/10.5555/563998.564029openalex-snapshot
Reducing the complexity of the register file in dynamic superscalar processors
inferredcites →https://doi.org/10.5555/774861.774880openalex-snapshot
Reducing register ports for higher speed and lower energy

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/cpe.3906openalex-snapshot
A survey of techniques for designing and managing CPU register file
inferred← citeshttps://doi.org/10.1007/11574859_1openalex-snapshot
An Optimized Front-End Physical Register File with Banking and Writeback Filtering
inferred← citeshttps://doi.org/10.1007/11847083_46openalex-snapshot
Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors
inferred← citeshttps://doi.org/10.1007/978-3-540-77704-5_6openalex-snapshot
Decoupled State-Execute Architecture
inferred← citeshttps://doi.org/10.1007/978-3-642-22333-4_7openalex-snapshot
IO-Aware Custom Instruction Exploration for Customizing Embedded Processors
inferred← citeshttps://doi.org/10.1007/s11227-013-1075-8openalex-snapshot
Customized pipeline and instruction set architecture for embedded processing engines
inferred← citeshttps://doi.org/10.1016/j.micpro.2006.08.001openalex-snapshot
Register port complexity reduction in wide-issue processors with selective instruction execution
inferred← citeshttps://doi.org/10.1016/j.micpro.2006.08.004openalex-snapshot
Compacting register file via 2-level renaming and bit-partitioning
inferred← citeshttps://doi.org/10.1016/j.parco.2010.08.005openalex-snapshot
Compiler-assisted power optimization for clustered VLIW architectures
inferred← citeshttps://doi.org/10.1023/b:ijpp.0000004510.66751.2eopenalex-snapshot
Power-Aware Compilation for Register File Energy Reduction
inferred← citeshttps://doi.org/10.1093/comjnl/bxh157openalex-snapshot
Instruction Level Parallelism through Microthreading—A Scalable Approach to Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/cahpc.2005.18openalex-snapshot
Chained In-Order/Out-of-Order DoubleCore Architecture
inferred← citeshttps://doi.org/10.1109/icasic.2005.1611275openalex-snapshot
Duplicated Register File Design for Embedded Simultaneous Multithreading Microprocessor
inferred← citeshttps://doi.org/10.1109/iccd.2003.1240920openalex-snapshot
Distributed reorder buffer schemes for low power
inferred← citeshttps://doi.org/10.1109/icpp.2006.20openalex-snapshot
Address-Value Decoupling for Early Register Deallocation
inferred← citeshttps://doi.org/10.1109/icsamos.2010.5642055openalex-snapshot
Energy-aware design space exploration of registerfile for extensible processors
inferred← citeshttps://doi.org/10.1109/iscas.2007.378798openalex-snapshot
Higher Clock Rate at Comparable IPC Through Reduced Circuit Complexity in Instruction Format Based Pipeline Clustering
inferred← citeshttps://doi.org/10.1109/islped.2015.7273490openalex-snapshot
Bank stealing for conflict mitigation in GPGPU Register File
inferred← citeshttps://doi.org/10.1109/isvlsi.2007.62openalex-snapshot
Investigating Simple Low Latency Reliable Multiported Register Files
inferred← citeshttps://doi.org/10.1109/itng.2006.73openalex-snapshot
Instruction Format Based Selective Execution for Register Port Complexity Reduction in High-Performance Processors
inferred← citeshttps://doi.org/10.1109/micro.2004.29openalex-snapshot
Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure
inferred← citeshttps://doi.org/10.1109/micro.2004.8openalex-snapshot
Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy
inferred← citeshttps://doi.org/10.1109/micro.2008.4771775openalex-snapshot
A distributed processor state management architecture for large-window processors
inferred← citeshttps://doi.org/10.1109/sbac-pad.2007.35openalex-snapshot
Register File Energy Optimization for Snooping Based Clustered VLIW Architectures
inferred← citeshttps://doi.org/10.1109/southeastcon44009.2020.9368300openalex-snapshot
Execution Array Memory Array Processor (XarMa)
inferred← citeshttps://doi.org/10.1109/tc.2004.11openalex-snapshot
Isolating short-lived operands for energy reduction
inferred← citeshttps://doi.org/10.1109/tc.2005.88openalex-snapshot
A Speculative Control Scheme for an Energy-Efficient Banked Register File
inferred← citeshttps://doi.org/10.1109/tc.2006.154openalex-snapshot
Throttling-Based Resource Management in High Performance Multithreaded Architectures
inferred← citeshttps://doi.org/10.1109/tc.2007.70785openalex-snapshot
Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption
inferred← citeshttps://doi.org/10.1109/tcad.2008.923254openalex-snapshot
Register File Power Reduction Using Bypass Sensitive Compiler
inferred← citeshttps://doi.org/10.1109/tpds.2007.70742openalex-snapshot
Operand-Load-Based Split Pipeline Architecture for High Clock Rate and Commensurable IPC
inferred← citeshttps://doi.org/10.1109/tvlsi.2008.2000243openalex-snapshot
Selective Writeback: Reducing Register File Pressure and Energy Consumption
inferred← citeshttps://doi.org/10.1109/tvlsi.2016.2584623openalex-snapshot
Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU
inferred← citeshttps://doi.org/10.1145/1028176.1006727openalex-snapshot
A Content Aware Integer Register File Organization
inferred← citeshttps://doi.org/10.1145/1088149.1088158openalex-snapshot
An asymmetric clustered processor based on value content
inferred← citeshttps://doi.org/10.1145/1134650.1134675openalex-snapshot
Bypass aware instruction scheduling for register file power reduction
inferred← citeshttps://doi.org/10.1145/1152154.1152194openalex-snapshot
SPARTAN
inferred← citeshttps://doi.org/10.1145/1159974.1134675openalex-snapshot
Bypass aware instruction scheduling for register file power reduction
inferred← citeshttps://doi.org/10.1145/1165573.1165584openalex-snapshot
Selective writeback
inferred← citeshttps://doi.org/10.1145/2000064.2000068openalex-snapshot
CRIB
inferred← citeshttps://doi.org/10.1145/2533397openalex-snapshot
Shared-port register file architecture for low-energy VLIW processors
inferred← citeshttps://doi.org/10.1145/871506.871564openalex-snapshot
Reducing reorder buffer complexity through selective operand caching
inferred← citeshttps://doi.org/10.1145/871506.871602openalex-snapshot
The microarchitecture of a low power register file
inferred← citeshttps://doi.org/10.20868/upm.thesis.83openalex-snapshot
Power estimation and power optimization policies for processor-based systems
inferred← citeshttps://doi.org/10.5555/942806.943844openalex-snapshot
Reducing datapath energy through the isolation of short-lived operands
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