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Fire-and-Forget: Load/Store Scheduling with No Store Queue at All

https://doi.org/10.1109/micro.2006.26
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1023/a:1018776132598openalex-snapshot
Speculative Memory Cloaking and Bypassing
inferredcites →https://doi.org/10.1109/12.509907openalex-snapshot
ARB: a hardware mechanism for dynamic reordering of memory references
inferredcites →https://doi.org/10.1109/2.982917openalex-snapshot
SimpleScalar: an infrastructure for computer system modeling
inferredcites →https://doi.org/10.1109/hpca.2005.42openalex-snapshot
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
inferredcites →https://doi.org/10.1109/hpca.2006.1598113openalex-snapshot
Store Vectors for Scalable Memory Dependence Prediction and Scheduling
inferredcites →https://doi.org/10.1109/isca.1998.694770openalex-snapshot
Memory dependence prediction using store sets
inferredcites →https://doi.org/10.1109/isca.2004.1310766openalex-snapshot
Memory ordering: a value-based approach
inferredcites →https://doi.org/10.1109/isca.2005.48openalex-snapshot
Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization
inferredcites →https://doi.org/10.1109/ispass.2001.990668openalex-snapshot
MASE: a novel infrastructure for detailed microarchitectural modeling
inferredcites →https://doi.org/10.1109/micro.1997.645814openalex-snapshot
Streamlining inter-operation memory communication via data dependence prediction
inferredcites →https://doi.org/10.1109/micro.1997.645830openalex-snapshot
MediaBench: a tool for evaluating and synthesizing multimedia and communications systems
inferredcites →https://doi.org/10.1109/micro.2000.898055openalex-snapshot
Silent stores for free
inferredcites →https://doi.org/10.1109/micro.2005.10openalex-snapshot
Address-Indexed Memory Disambiguation and Store-to-Load Forwarding
inferredcites →https://doi.org/10.1109/micro.2005.29openalex-snapshot
Scalable Store-Load Forwarding via Store Queue Index Prediction
inferredcites →https://doi.org/10.1109/micro.2006.39openalex-snapshot
NoSQ: Store-Load Communication without a Store Queue
inferredcites →https://doi.org/10.1109/mm.2004.87openalex-snapshot
Scalable hardware memory disambiguation for high-ILP processors
inferredcites →https://doi.org/10.1109/pact.2003.1238020openalex-snapshot
Picking statistically valid and early simulation points
inferredcites →https://doi.org/10.1109/wwc.2001.15openalex-snapshot
MiBench: A free, commercially representative embedded benchmark suite
inferredcites →https://doi.org/10.1109/wwc.2001.990739openalex-snapshot
MiBench: A free, commercially representative embedded benchmark suite
inferredcites →https://doi.org/10.1145/1028176.1006709openalex-snapshot
Memory Ordering
inferredcites →https://doi.org/10.1145/1080695.1070008openalex-snapshot
Store Vulnerability Window (SVW)
inferredcites →https://doi.org/10.1145/1080695.1070009openalex-snapshot
Store Buffer Design in First-Level Multibanked Data Caches
inferredcites →https://doi.org/10.1145/178243.178446openalex-snapshot
Efficient detection of all pointer and array access errors
inferredcites →https://doi.org/10.1145/279358.279378openalex-snapshot
Memory dependence prediction using store sets
inferredcites →https://doi.org/10.1145/356989.357003openalex-snapshot
Frequent value locality and value-centric data cache design
inferredcites →https://doi.org/10.1145/360128.360133openalex-snapshot
Silent stores for free
inferredcites →https://doi.org/10.1145/378993.379235openalex-snapshot
Frequent value locality and value-centric data cache design
inferredcites →https://doi.org/10.1147/rd.502.0287openalex-snapshot
Decomposing the load-store queue by function for power reduction and scalability
inferredcites →https://doi.org/10.5555/266800.266823openalex-snapshot
Streamlining inter-operation memory communication via data dependence prediction
inferredcites →https://doi.org/10.5555/942806.943854openalex-snapshot
Picking statistically valid and early simulation points

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/s11265-009-0412-xopenalex-snapshot
An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors
inferred← citeshttps://doi.org/10.1007/s11390-012-1263-7openalex-snapshot
Active Store Window: Enabling Far Store-Load Forwarding with Scalability and Complexity-Efficiency
inferred← citeshttps://doi.org/10.1109/hpca.2008.4658634openalex-snapshot
PEEP: Exploiting predictability of memory dependences in SMT processors
inferred← citeshttps://doi.org/10.1109/hpca.2009.4798280openalex-snapshot
Criticality-based optimizations for efficient load processing
inferred← citeshttps://doi.org/10.1109/hpca.2011.5749755openalex-snapshot
Dynamically Specialized Datapaths for energy efficient computing
inferred← citeshttps://doi.org/10.1109/hpca.2018.00066openalex-snapshot
NACHOS: Software-Driven Hardware-Assisted Memory Disambiguation for Accelerators
inferred← citeshttps://doi.org/10.1109/iccd.2007.4601888openalex-snapshot
A position-insensitive finished store buffer
inferred← citeshttps://doi.org/10.1109/iccd.2012.6378654openalex-snapshot
SOLE: Speculative one-cycle load execution with scalability, high-performance and energy-efficiency
inferred← citeshttps://doi.org/10.1109/icoin68469.2026.11480646openalex-snapshot
NimbusGuard: A Novel Framework for Proactive Kubernetes Autoscaling Using Deep Q-Networks
inferred← citeshttps://doi.org/10.1109/isca.2008.10openalex-snapshot
A Two-Level Load/Store Queue Based on Execution Locality
inferred← citeshttps://doi.org/10.1109/isca.2008.6openalex-snapshot
Counting Dependence Predictors
inferred← citeshttps://doi.org/10.1109/isca.2018.00029openalex-snapshot
Dynamic Memory Dependence Predication
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00127openalex-snapshot
SSBench: Automated Characterization of Memory Dependence Predictors on Modern CPUs
inferred← citeshttps://doi.org/10.1109/lca.2016.2628379openalex-snapshot
Storage-Free Memory Dependency Prediction
inferred← citeshttps://doi.org/10.1109/micro.2006.39openalex-snapshot
NoSQ: Store-Load Communication without a Store Queue
inferred← citeshttps://doi.org/10.1109/micro.2016.7783741openalex-snapshot
PoisonIvy: Safe speculation for secure memory
inferred← citeshttps://doi.org/10.1109/mm.2007.17openalex-snapshot
NoSQ: Store-Load Communication without a Store Queue
inferred← citeshttps://doi.org/10.1109/pact.2007.10openalex-snapshot
A Scalable Low Power Store Queue for Large InstructionWindow Processors
inferred← citeshttps://doi.org/10.1109/pact.2009.29openalex-snapshot
Zero-Value Caches: Cancelling Loads that Return Zero
inferred← citeshttps://doi.org/10.1109/sips.2009.5336266openalex-snapshot
Register file exploration for a multi-standard wireless forward error correction ASIP
inferred← citeshttps://doi.org/10.1109/tc.2008.146openalex-snapshot
Replacing Associative Load Queues: A Timing-Centric Approach
inferred← citeshttps://doi.org/10.1109/tc.2010.131openalex-snapshot
Macro Data Load: An Efficient Mechanism for Enhancing Loaded Data Reuse
inferred← citeshttps://doi.org/10.1145/1250662.1250696openalex-snapshot
Mechanisms for store-wait-free multiprocessors
inferred← citeshttps://doi.org/10.1145/1250662.1250705openalex-snapshot
Late-binding
inferred← citeshttps://doi.org/10.1145/1273440.1250696openalex-snapshot
Mechanisms for store-wait-free multiprocessors
inferred← citeshttps://doi.org/10.1145/1273440.1250705openalex-snapshot
Late-binding
inferred← citeshttps://doi.org/10.1145/1366230.1366261openalex-snapshot
A modular 3d processor for flexible product design and technology migration
inferred← citeshttps://doi.org/10.1145/1394608.1382140openalex-snapshot
Counting Dependence Predictors
inferred← citeshttps://doi.org/10.1145/1394608.1382171openalex-snapshot
A Two-Level Load/Store Queue Based on Execution Locality
inferred← citeshttps://doi.org/10.1145/1509084.1509087openalex-snapshot
Zero loads
inferred← citeshttps://doi.org/10.1145/1555754.1555786openalex-snapshot
Decoupled store completion/silent deterministic replay
inferred← citeshttps://doi.org/10.1145/1555815.1555786openalex-snapshot
Decoupled store completion/silent deterministic replay
inferred← citeshttps://doi.org/10.1145/1880043.1880046openalex-snapshot
Federation
inferred← citeshttps://doi.org/10.1145/2038698.2038710openalex-snapshot
A unified approach to eliminate memory accesses early
inferred← citeshttps://doi.org/10.1145/2597917.2597940openalex-snapshot
SAMO
inferred← citeshttps://doi.org/10.1145/2749469.2750390openalex-snapshot
Efficient execution of memory access phases using dataflow specialization
inferred← citeshttps://doi.org/10.1145/2800787openalex-snapshot
Revisiting Clustered Microarchitecture for Future Superscalar Cores
inferred← citeshttps://doi.org/10.1145/2872887.2750390openalex-snapshot
Efficient execution of memory access phases using dataflow specialization
inferred← citeshttps://doi.org/10.1145/3243176.3243208openalex-snapshot
Cost effective speculation with the omnipredictor
inferred← citeshttps://doi.org/10.1145/3280848openalex-snapshot
Static Prediction of Silent Stores
inferred← citeshttps://doi.org/10.1145/3307650.3322269openalex-snapshot
Filter caching for free
inferred← citeshttps://doi.org/10.1145/3658644.3690214openalex-snapshot
SemPat: From Hyperproperties to Attack Patterns for Scalable Analysis of Microarchitectural Security
inferred← citeshttps://doi.org/10.1587/transele.e98.c.580openalex-snapshot
Address Order Violation Detection with Parallel Counting Bloom Filters
inferred← citeshttps://doi.org/10.23919/date64628.2025.10993073openalex-snapshot
PreVV: Eliminating Store Queue via Premature Value Validation for Dataflow Circuit on FPGA
inferred← citeshttps://doi.org/10.5555/3195638.3195684openalex-snapshot
Poisonivy: safe speculation for secure memory
inferred← citeshttps://doi.org/10.5821/dissertation-2117-93339openalex-snapshot
Affordable kilo-instruction processors
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95043openalex-snapshot
Design of a distributed memory unit for clustered microarchitectures
inferred← citeshttps://doi.org/10.70675/9cf1b1cdz4744z49b5z9bc2zdd9658d77063openalex-snapshot
Revisiting Wide Superscalar Microarchitecture
inferred← citeshttps://doi.org/10.70675/ccab0a2bzc2b2z4162z9c58z4bc732cc2622openalex-snapshot
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