On the public citation graph

Exploiting Vector Parallelism in Software Pipelined Loops

https://doi.org/10.1109/micro.2005.20
0 signed · 63 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1002/j.1538-7305.1970.tb01770.xopenalex-snapshot
An Efficient Heuristic Procedure for Partitioning Graphs
inferredcites →https://doi.org/10.1007/bf03356742openalex-snapshot
Iterative Modulo Scheduling
inferredcites →https://doi.org/10.1023/a:1007507005174openalex-snapshot
Compilation Techniques for Multimedia Processors
inferredcites →https://doi.org/10.1023/a:1007559022013openalex-snapshot
A Vectorizing Compiler for Multimedia Extensions
inferredcites →https://doi.org/10.1109/40.526921openalex-snapshot
VIS speeds new media processing
inferredcites →https://doi.org/10.1109/40.526925openalex-snapshot
Subword parallelism with MAX-2
inferredcites →https://doi.org/10.1109/40.820055openalex-snapshot
The TigerSHARC DSP architecture
inferredcites →https://doi.org/10.1109/40.848475openalex-snapshot
AltiVec extension to PowerPC accelerates media processing
inferredcites →https://doi.org/10.1109/40.865866openalex-snapshot
Implementing streaming SIMD extensions on the Pentium III processor
inferredcites →https://doi.org/10.1109/cgo.2005.18openalex-snapshot
Efficient SIMD Code Generation for Runtime Alignment and Length Conversion
inferredcites →https://doi.org/10.1109/cgo.2005.33openalex-snapshot
Superword-Level Parallelism in the Presence of Control Flow
inferredcites →https://doi.org/10.1109/ispass.2005.1430573openalex-snapshot
Scalarization on Short Vector Machines
inferredcites →https://doi.org/10.1109/micro.1992.697012openalex-snapshot
Code Generation Schema For Modulo Scheduled Loops
inferredcites →https://doi.org/10.1109/micro.1995.476825openalex-snapshot
Register allocation for predicated code
inferredcites →https://doi.org/10.1109/micro.1996.566456openalex-snapshot
Modulo scheduling of loops in control-intensive non-numeric programs
inferredcites →https://doi.org/10.1109/micro.1998.742773openalex-snapshot
Effective cluster assignment for modulo scheduling
inferredcites →https://doi.org/10.1109/micro.2001.991115openalex-snapshot
Modulo scheduling with integrated register spilling for clustered VLIW architectures
inferredcites →https://doi.org/10.1109/mm.2003.1196114openalex-snapshot
Itanium 2 processor microarchitecture
inferredcites →https://doi.org/10.1109/pact.1999.807510openalex-snapshot
On the complexity of loop fusion
inferredcites →https://doi.org/10.1109/pact.2001.953298openalex-snapshot
A unified modulo scheduling and register allocation technique for clustered processors
inferredcites →https://doi.org/10.1109/pact.2002.1105970openalex-snapshot
Increasing and detecting memory address congruence
inferredcites →https://doi.org/10.1109/pact.2002.1106003openalex-snapshot
Compiler-controlled caching in superword register files for multimedia extension architectures
inferredcites →https://doi.org/10.1137/0201010openalex-snapshot
Depth-First Search and Linear Graph Algorithms
inferredcites →https://doi.org/10.1145/1065910.1065931openalex-snapshot
Generation of permutations for SIMD processors
inferredcites →https://doi.org/10.1145/1088149.1088172openalex-snapshot
An integrated simdization framework using virtual vectors
inferredcites →https://doi.org/10.1145/143095.143141openalex-snapshot
Register allocation for software pipelined loops
inferredcites →https://doi.org/10.1145/144965.145795openalex-snapshot
Code generation schema for modulo scheduled loops
inferredcites →https://doi.org/10.1145/155090.155115openalex-snapshot
Lifetime-sensitive modulo scheduling
inferredcites →https://doi.org/10.1145/192724.192731openalex-snapshot
Iterative modulo scheduling
inferredcites →https://doi.org/10.1145/193209.193217openalex-snapshot
SUIF
inferredcites →https://doi.org/10.1145/349299.349320openalex-snapshot
Exploiting superword level parallelism with multimedia instruction sets
inferredcites →https://doi.org/10.1145/53990.54022openalex-snapshot
Software pipelining: an effective scheduling technique for VLIW machines
inferredcites →https://doi.org/10.1145/567067.567085openalex-snapshot
Conversion of control dependence to data dependence
inferredcites →https://doi.org/10.1145/567532.567555openalex-snapshot
Dependence graphs and compiler optimizations
inferredcites →https://doi.org/10.1145/68182.68185openalex-snapshot
Overlapped loop support in the Cydra 5
inferredcites →https://doi.org/10.1145/951710.951714openalex-snapshot
Vectorizing for a SIMdD DSP architecture
inferredcites →https://doi.org/10.1145/989393.989420openalex-snapshot
Software pipelining
inferredcites →https://doi.org/10.1145/996841.996853openalex-snapshot
Vectorization for SIMD architectures with alignment constraints
inferredcites →https://doi.org/10.5555/225160.225210openalex-snapshot
Stage scheduling: a technique to reduce the register requirements of a module schedule
inferredcites →https://doi.org/10.5555/243846.243879openalex-snapshot
Modulo scheduling of loops in control-intensive non-numeric programs
inferredcites →https://doi.org/10.5555/290940.290966openalex-snapshot
Effective cluster assignment for modulo scheduling
inferredcites →https://doi.org/10.5555/520793.825721openalex-snapshot
On the complexity of loop fusion
inferredcites →https://doi.org/10.5555/563998.564019openalex-snapshot
Graph-partitioning based instruction scheduling for clustered processors
inferredcites →https://doi.org/10.5555/563998.564020openalex-snapshot
Modulo scheduling with integrated register spilling for clustered VLIW architectures
inferredcites →https://doi.org/10.5555/645988.674300openalex-snapshot
A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors
inferredcites →https://doi.org/10.5555/645989.674329openalex-snapshot
Increasing and detecting memory address congruence

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-540-74742-0_83openalex-snapshot
Instruction Selection for Subword Level Parallelism Optimizations for Application Specific Instruction Processors
inferred← citeshttps://doi.org/10.1007/978-3-642-13374-9_7openalex-snapshot
Mapping Streaming Languages to General Purpose Processors through Vectorization
inferred← citeshttps://doi.org/10.1007/978-3-642-19861-8_13openalex-snapshot
Data Layout Transformation for Stencil Computations on Short-Vector SIMD Architectures
inferred← citeshttps://doi.org/10.1007/s11265-008-0170-1openalex-snapshot
Applying Data Mapping Techniques to Vector DSPs
inferred← citeshttps://doi.org/10.1007/s13198-019-00799-5openalex-snapshot
Analysis of cache behaviour and software optimizations for faster on-chip network simulations
inferred← citeshttps://doi.org/10.1093/ietfec/e90-a.12.2800openalex-snapshot
Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram
inferred← citeshttps://doi.org/10.1109/hpca.2007.346199openalex-snapshot
Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping
inferred← citeshttps://doi.org/10.1109/iciinfs.2016.8262912openalex-snapshot
Cache analysis and software optimizations for faster on-chip network simulations
inferred← citeshttps://doi.org/10.1109/icsamos.2007.4285727openalex-snapshot
Applying Data Mapping Techniques to Vector DSPs
inferred← citeshttps://doi.org/10.1109/micro.2010.38openalex-snapshot
Efficient Selection of Vector Instructions Using Dynamic Programming
inferred← citeshttps://doi.org/10.1145/1183401.1183422openalex-snapshot
Implementing virtual memory in a vector processor with software restart markers
inferred← citeshttps://doi.org/10.1145/1356058.1356085openalex-snapshot
Compiling for vector-thread architectures
inferred← citeshttps://doi.org/10.1145/2145816.2145824openalex-snapshot
Efficient SIMD code generation for irregular kernels
inferred← citeshttps://doi.org/10.1145/2370036.2145824openalex-snapshot
Efficient SIMD code generation for irregular kernels
inferred← citeshttps://doi.org/10.1145/3411029.3411033openalex-snapshot
Leveraging SIMD parallelism for accelerating network applications
inferred← citeshttps://doi.org/10.21817/ijet/2018/v10i3/181003098openalex-snapshot
Intrinsic Compilation Model to enhance Performance of real time application in embedded multi core system
inferred← citeshttps://doi.org/10.70675/2a7514afzb62bz4f55zbbb9zae5d63ed5f8fopenalex-snapshot
SIMD-aware word length optimization for floating-point to fixed-point conversion targeting embedded processors
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.