On the public citation graph
Increasing and detecting memory address congruence
0 signed · 62 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/hipc.1998.737991openalex-snapshot
Memory bank disambiguation using modulo unrolling for Raw machines
inferredcites →https://doi.org/10.1145/143365.143493openalex-snapshot
Predicting conditional branch directions from previous runs of a program
inferredcites →https://doi.org/10.1145/285930.285985openalex-snapshot
Very long instruction work architectures and the ELI-512
inferredcites →https://doi.org/10.1145/349299.349320openalex-snapshot
Exploiting superword level parallelism with multimedia instruction sets
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cpe.3424openalex-snapshot
Evaluating vector data type usage in OpenCL kernels
inferred← citeshttps://doi.org/10.1007/978-1-4419-1176-6openalex-snapshot
C Compilers for ASIPs: Automatic Compiler Generation with LISA
inferred← citeshttps://doi.org/10.1007/978-3-540-24644-2_2openalex-snapshot
Adapting Convergent Scheduling Using Machine-Learning
inferred← citeshttps://doi.org/10.1007/978-3-540-24644-2_27openalex-snapshot
A Preliminary Study on the Vectorization of Multimedia Applications for Multimedia Extensions
inferred← citeshttps://doi.org/10.1007/978-3-540-71229-9_1openalex-snapshot
New Algorithms for SIMD Alignment
inferred← citeshttps://doi.org/10.1007/978-3-540-71410-1_16openalex-snapshot
Grids: A Domain for Analyzing the Distribution of Numerical Values
inferred← citeshttps://doi.org/10.1007/978-3-642-19861-8_13openalex-snapshot
Data Layout Transformation for Stencil Computations on Short-Vector SIMD Architectures
inferred← citeshttps://doi.org/10.1007/s10766-008-0071-8openalex-snapshot
A Case Study on Compiler Optimizations for the Intel® CoreTM 2 Duo Processor
inferred← citeshttps://doi.org/10.1007/s11265-013-0754-2openalex-snapshot
Loop Transforming for Reducing Data Alignment on Multi-Core SIMD Processors
inferred← citeshttps://doi.org/10.1016/j.parco.2013.06.004openalex-snapshot
Efficient multimedia coprocessor with enhanced SIMD engines for exploiting ILP and DLP
inferred← citeshttps://doi.org/10.1093/comjnl/bxm099openalex-snapshot
A Review of SIMD Multimedia Extensions and their Usage in Scientific and Engineering Applications
inferred← citeshttps://doi.org/10.1109/cgo.2005.18openalex-snapshot
Efficient SIMD Code Generation for Runtime Alignment and Length Conversion
inferred← citeshttps://doi.org/10.1109/cgo.2005.33openalex-snapshot
Superword-Level Parallelism in the Presence of Control Flow
inferred← citeshttps://doi.org/10.1109/cgo.2006.25openalex-snapshot
Multi-platform Auto-vectorization
inferred← citeshttps://doi.org/10.1109/cgo.2011.5764683openalex-snapshot
Vapor SIMD: Auto-vectorize once, run everywhere
inferred← citeshttps://doi.org/10.1109/em-com.2009.5403000openalex-snapshot
Implicit Data Permutation for SIMD Devices
inferred← citeshttps://doi.org/10.1109/hpca.2003.1183551openalex-snapshot
Scalar operand networks: on-chip interconnect for ILP in partitioned architectures
inferred← citeshttps://doi.org/10.1109/hpca.2010.5416631openalex-snapshot
SIF: Overcoming the limitations of SIMD devices via implicit permutation
inferred← citeshttps://doi.org/10.1109/hpca.2010.5463057openalex-snapshot
DMA++: on the fly data realignment for on-chip memories
inferred← citeshttps://doi.org/10.1109/icppw.2006.57openalex-snapshot
Multidimensional Dataflow-based Parallelization for Multimedia Instruction Set Extensions
inferred← citeshttps://doi.org/10.1109/ipdps.2005.94openalex-snapshot
An empirical study on the vectorization of multimedia applications for multimedia extensions
inferred← citeshttps://doi.org/10.1109/ipdps.2007.370641openalex-snapshot
Model-Guided Empirical Optimization for Multimedia Extension Architectures: A Case Study
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00024openalex-snapshot
T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware
inferred← citeshttps://doi.org/10.1109/iscas.2010.5537700openalex-snapshot
Permutation optimization for SIMD devices
inferred← citeshttps://doi.org/10.1109/micro.2005.20openalex-snapshot
Exploiting Vector Parallelism in Software Pipelined Loops
inferred← citeshttps://doi.org/10.1109/micro.2010.38openalex-snapshot
Efficient Selection of Vector Instructions Using Dynamic Programming
inferred← citeshttps://doi.org/10.1109/pact.2005.33openalex-snapshot
Optimizing Compiler for the CELL Processor
inferred← citeshttps://doi.org/10.1109/snpd.2015.7176233openalex-snapshot
Data layout transformation for structure vectorization on SIMD architectures
inferred← citeshttps://doi.org/10.1109/tc.2010.255openalex-snapshot
DMA++: On the Fly Data Realignment for On-Chip Memories
inferred← citeshttps://doi.org/10.1145/1065910.1065931openalex-snapshot
Generation of permutations for SIMD processors
inferred← citeshttps://doi.org/10.1145/1070891.1065931openalex-snapshot
Generation of permutations for SIMD processors
inferred← citeshttps://doi.org/10.1145/1133255.1133996openalex-snapshot
Optimizing data permutations for SIMD devices
inferred← citeshttps://doi.org/10.1145/1133981.1133996openalex-snapshot
Optimizing data permutations for SIMD devices
inferred← citeshttps://doi.org/10.1145/1254766.1254809openalex-snapshot
Compiler-managed partitioned data caches for low power
inferred← citeshttps://doi.org/10.1145/1273444.1254809openalex-snapshot
Compiler-managed partitioned data caches for low power
inferred← citeshttps://doi.org/10.1145/1450095.1450121openalex-snapshot
Efficient vectorization of SIMD programs with non-aligned and irregular data access hardware
inferred← citeshttps://doi.org/10.1145/1509864.1509866openalex-snapshot
A SIMD optimization framework for retargetable compilers
inferred← citeshttps://doi.org/10.1145/2086696.2086729openalex-snapshot
Using machine learning to improve automatic vectorization
inferred← citeshttps://doi.org/10.1145/2854038.2854054openalex-snapshot
Exploiting mixed SIMD parallelism by reducing data reorganization overhead
inferred← citeshttps://doi.org/10.1145/2886101openalex-snapshot
A Compiler Approach for Exploiting Partial SIMD Parallelism
inferred← citeshttps://doi.org/10.1145/996841.996853openalex-snapshot
Vectorization for SIMD architectures with alignment constraints
inferred← citeshttps://doi.org/10.5555/2755753.2757058openalex-snapshot
A basic linear algebra compiler for embedded processors
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94621openalex-snapshot
Software caching techniques and hardware optimizations for on-chip local memories
inferred← citeshttps://doi.org/10.5821/dissertation-2117-96011openalex-snapshot
SIMD@OpenMP : a programming model approach to leverage SIMD features
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.