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Managing Distributed, Shared L2 Caches through OS-Level Page Allocation
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/2.982917openalex-snapshot
SimpleScalar: an infrastructure for computer system modeling
inferredcites →https://doi.org/10.1109/hpca.1996.501175openalex-snapshot
The impact of shared-cache clustering in small-scale shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/hpca.2004.10017openalex-snapshot
Organizing the Last Line of Defense before Hitting the Memory Wall for CMPs
inferredcites →https://doi.org/10.1109/hpca.2005.27openalex-snapshot
Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture
inferredcites →https://doi.org/10.1109/isca.1994.288152openalex-snapshot
Exploring the design space for a shared-cache multiprocessor
inferredcites →https://doi.org/10.1109/isca.1995.524546openalex-snapshot
The SPLASH-2 programs: characterization and methodological considerations
inferredcites →https://doi.org/10.1109/isca.2005.39openalex-snapshot
Optimizing Replication, Communication, and Capacity Allocation in CMPs
inferredcites →https://doi.org/10.1109/isca.2005.53openalex-snapshot
Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors
inferredcites →https://doi.org/10.1109/mc.1997.612248openalex-snapshot
Billion-Transistor Architectures
inferredcites →https://doi.org/10.1109/mc.2004.1273999openalex-snapshot
Billion-transistor architectures: there and back again
inferredcites →https://doi.org/10.1109/micro.2004.21openalex-snapshot
Managing Wire Delay in Large Chip-Multiprocessor Caches
inferredcites →https://doi.org/10.1109/mm.2005.35openalex-snapshot
Niagara: A 32-Way Multithreaded Sparc Processor
inferredcites →https://doi.org/10.1109/pact.2001.953300openalex-snapshot
Exploring the design space of future CMPs
inferredcites →https://doi.org/10.1145/1080695.1070001openalex-snapshot
Optimizing Replication, Communication, and Capacity Allocation in CMPs
inferredcites →https://doi.org/10.1145/1088149.1088154openalex-snapshot
A NUCA substrate for flexible CMP cache sharing
inferredcites →https://doi.org/10.1145/1150019.1136509openalex-snapshot
Cooperative Caching for Chip Multiprocessors
inferredcites →https://doi.org/10.1145/1178597.1178613openalex-snapshot
A flexible data to L2 cache mapping approach for future multicore processors
inferredcites →https://doi.org/10.1145/118544.118546openalex-snapshot
Experimental comparison of memory management policies for NUMA multiprocessors
inferredcites →https://doi.org/10.1145/138873.138876openalex-snapshot
Page placement algorithms for large real-indexed caches
inferredcites →https://doi.org/10.1145/191995.192026openalex-snapshot
Exploring the design space for a shared-cache multiprocessor
inferredcites →https://doi.org/10.1145/237090.237205openalex-snapshot
Operating system support for improving data locality on CC-NUMA compute servers
inferredcites →https://doi.org/10.1145/305138.305189openalex-snapshot
Reducing cache misses using hardware and software page placement
inferredcites →https://doi.org/10.1145/362686.362692openalex-snapshot
Space/time trade-offs in hash coding with allowable errors
inferredcites →https://doi.org/10.1145/605397.605420openalex-snapshot
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
inferredcites →https://doi.org/10.1145/74850.74855openalex-snapshot
The implementation of a coherent memory abstraction on a NUMA multiprocessor: experiences with platinum
inferredcites →https://doi.org/10.5555/645988.674164openalex-snapshot
Exploring the Design Space of Future CMPs
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/9781119973584.ch13openalex-snapshot
Cooperative Caching for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1002/cpe.3172openalex-snapshot
A real‐time capable coherent data cache for multicores
inferred← citeshttps://doi.org/10.1002/cpe.3871openalex-snapshot
A dedicated private‐shared cache design for scalable multiprocessors
inferred← citeshttps://doi.org/10.1002/spe.956openalex-snapshot
Two‐phase trace‐driven simulation (TPTS): a fast multicore processor architecture simulation approach
inferred← citeshttps://doi.org/10.1007/978-3-031-01734-6openalex-snapshot
Multi-Core Cache Hierarchies
inferred← citeshttps://doi.org/10.1007/978-3-319-03859-9_23openalex-snapshot
Coordinate Task and Memory Management for Improving Power Efficiency
inferred← citeshttps://doi.org/10.1007/978-3-319-27119-4_13openalex-snapshot
DBFS: Dual Best-First Search Mapping Algorithm for Shared-Cache Multicore Processors
inferred← citeshttps://doi.org/10.1007/978-3-540-92990-1_26openalex-snapshot
ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors
inferred← citeshttps://doi.org/10.1007/978-3-642-17313-4_53openalex-snapshot
Multi-core Architecture Cache Performance Analysis and Optimization Based on Distributed Method
inferred← citeshttps://doi.org/10.1007/978-3-642-21931-3_38openalex-snapshot
Page Coloring Synchronization for Improving Cache Performance in Virtualization Environment
inferred← citeshttps://doi.org/10.1007/978-3-642-32820-6_24openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-642-40047-6_20openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-94-007-1679-7_5openalex-snapshot
Energy-Aware On-Chip Networks
inferred← citeshttps://doi.org/10.1007/s10766-011-0178-1openalex-snapshot
Managing Data Placement in Memory Systems with Multiple Memory Controllers
inferred← citeshttps://doi.org/10.1007/s10766-014-0334-5openalex-snapshot
A Phase Behavior Aware Dynamic Cache Partitioning Scheme for CMPs
inferred← citeshttps://doi.org/10.1007/s11227-013-0939-2openalex-snapshot
Virtual machine consolidation based on interference modeling
inferred← citeshttps://doi.org/10.1007/s11227-014-1325-4openalex-snapshot
DASC-DIR: a low-overhead coherence directory for many-core processors
inferred← citeshttps://doi.org/10.1007/s11227-015-1608-4openalex-snapshot
Locality-aware data replication in the last-level cache for large scale multicores
inferred← citeshttps://doi.org/10.1007/s11227-017-2181-9openalex-snapshot
OLM: online LLC management for container-based cloud service
inferred← citeshttps://doi.org/10.1007/s11227-019-02858-xopenalex-snapshot
FOS: a low-power cache organization for multicores
inferred← citeshttps://doi.org/10.1007/s11265-015-1015-3openalex-snapshot
PUMA: From Simultaneous to Parallel for Shared Memory System in Multi-core
inferred← citeshttps://doi.org/10.1007/s11390-010-9322-4openalex-snapshot
CCNoC: Cache-Coherent Network on Chip for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1016/b978-0-12-408089-8.00002-1openalex-snapshot
Understanding Application Contentiousness and Sensitivity on Modern Multicores
inferred← citeshttps://doi.org/10.1016/bs.adcom.2018.03.001openalex-snapshot
Dark Silicon and the History of Computing
inferred← citeshttps://doi.org/10.1016/j.future.2017.06.001openalex-snapshot
Exploring the relationship between architectures and management policies in the design of NUCA-based chip multicore systems
inferred← citeshttps://doi.org/10.1016/j.future.2019.11.024openalex-snapshot
An efficient cache flat storage organization for multithreaded workloads for low power processors
inferred← citeshttps://doi.org/10.1016/j.jnca.2015.08.001openalex-snapshot
PARS: A scheduling of periodically active rank to optimize power efficiency for main memory
inferred← citeshttps://doi.org/10.1016/j.jpdc.2010.11.009openalex-snapshot
C-AMTE: A location mechanism for flexible cache management in chip multiprocessors
inferred← citeshttps://doi.org/10.1016/j.jpdc.2011.03.005openalex-snapshot
Resolving a L2-prefetch-caused parallel nonscaling on Intel Core microarchitecture
inferred← citeshttps://doi.org/10.1016/j.micpro.2010.10.001openalex-snapshot
Virtualizing network-on-chip resources in chip-multiprocessors
inferred← citeshttps://doi.org/10.1016/j.micpro.2013.12.003openalex-snapshot
Reliability improvement in private non-uniform cache architecture using two enhanced structures for coherence protocols and replacement policies
inferred← citeshttps://doi.org/10.1016/j.micpro.2014.03.008openalex-snapshot
Runtime home mapping for effective memory resource usage
inferred← citeshttps://doi.org/10.1016/j.micpro.2015.11.020openalex-snapshot
Reconfigurable cache for real-time MPSoCs: Scheduling and implementation
inferred← citeshttps://doi.org/10.1016/j.microrel.2015.07.049openalex-snapshot
Design space exploration of non-uniform cache access for soft-error vulnerability mitigation
inferred← citeshttps://doi.org/10.1016/j.sysarc.2009.11.006openalex-snapshot
A scalable organization for distributed directories
inferred← citeshttps://doi.org/10.1016/j.sysarc.2012.03.001openalex-snapshot
Network-on-Chip virtualization in Chip-Multiprocessor Systems
inferred← citeshttps://doi.org/10.1109/access.2015.2507576openalex-snapshot
Dynamic Resource Partitioning for Heterogeneous Multi-Core-Based Cloud Computing in Smart Cities
inferred← citeshttps://doi.org/10.1109/access.2018.2883415openalex-snapshot
Optimization of the Load Balancing Policy for Tiled Many-Core Processors
inferred← citeshttps://doi.org/10.1109/access.2019.2895701openalex-snapshot
Analysis of Memory System of Tiled Many-Core Processors
inferred← citeshttps://doi.org/10.1109/access.2019.2939859openalex-snapshot
Cache-Aware Real-Time Virtualization for Clustered Multi-Core Platforms
inferred← citeshttps://doi.org/10.1109/aspdac.2012.6165002openalex-snapshot
Dynamic reusability-based replication with network address mapping in CMPs
inferred← citeshttps://doi.org/10.1109/bigdata.2016.7840762openalex-snapshot
SmartCache: Application layer caching to improve performance of large-scale memory mapping
inferred← citeshttps://doi.org/10.1109/ccgrid.2013.16openalex-snapshot
Flexible Capacity Partitioning in Many-Core Tiled CMPs
inferred← citeshttps://doi.org/10.1109/codes-isss.2013.6658988openalex-snapshot
Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache
inferred← citeshttps://doi.org/10.1109/cse.2014.347openalex-snapshot
Pseudo Share: Bring Shared to Exclusive for Main Memory in Multi-core Systems
inferred← citeshttps://doi.org/10.1109/date.2012.6176456openalex-snapshot
Dynamic Directories: A mechanism for reducing on-chip interconnect power in multicores
inferred← citeshttps://doi.org/10.1109/dsd.2015.56openalex-snapshot
Systematic Reverse Engineering of Cache Slice Selection in Intel Processors
inferred← citeshttps://doi.org/10.1109/dsn.2012.6263956openalex-snapshot
NINEPIN: Non-invasive and energy efficient performance isolation in virtualized servers
inferred← citeshttps://doi.org/10.1109/ecrts.2013.19openalex-snapshot
A Coordinated Approach for Practical OS-Level Cache Management in Multi-core Real-Time Systems
inferred← citeshttps://doi.org/10.1109/escience.2015.28openalex-snapshot
Early Experiences with Separate Caches for Private and Shared Data
inferred← citeshttps://doi.org/10.1109/fit.2011.26openalex-snapshot
Operating System-Aware Cache Optimization Techniques for Multi Core Processors
inferred← citeshttps://doi.org/10.1109/hipc.2009.5433220openalex-snapshot
Distance-aware round-robin mapping for large NUCA caches
inferred← citeshttps://doi.org/10.1109/hipc.2011.6152739openalex-snapshot
High performance cache block replication using re-reference probability in CMPs
inferred← citeshttps://doi.org/10.1109/hotchips.2013.7478320openalex-snapshot
Hardware-level thread migration in a 110-core shared-memory multiprocessor
inferred← citeshttps://doi.org/10.1109/hpca.2008.4658653openalex-snapshot
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems
inferred← citeshttps://doi.org/10.1109/hpca.2009.4798252openalex-snapshot
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
inferred← citeshttps://doi.org/10.1109/hpca.2009.4798258openalex-snapshot
PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches
inferred← citeshttps://doi.org/10.1109/hpca.2009.4798260openalex-snapshot
Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches
inferred← citeshttps://doi.org/10.1109/hpca.2009.4798261openalex-snapshot
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
inferred← citeshttps://doi.org/10.1109/hpca.2010.5416639openalex-snapshot
Towards scalable, energy-efficient, bus-based on-chip networks
inferred← citeshttps://doi.org/10.1109/hpca.2010.5416641openalex-snapshot
ESP-NUCA: A low-cost adaptive Non-Uniform Cache Architecture
inferred← citeshttps://doi.org/10.1109/hpca.2010.5416655openalex-snapshot
Understanding how off-chip memory bandwidth partitioning in Chip Multiprocessors affects system performance
inferred← citeshttps://doi.org/10.1109/hpca.2013.6522311openalex-snapshot
Application-to-core mapping policies to reduce memory system interference in multi-core systems
inferred← citeshttps://doi.org/10.1109/hpca.2013.6522318openalex-snapshot
Optimizing Google's warehouse scale computers: The NUMA experience
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056061openalex-snapshot
Scaling distributed cache hierarchies through computation and data co-scheduling
inferred← citeshttps://doi.org/10.1109/hpcc/smartcity/dss.2019.00265openalex-snapshot
Data Shepherding: A Last Level Cache Design for Large Scale Chips
inferred← citeshttps://doi.org/10.1109/iccad.2011.6105315openalex-snapshot
Improving shared cache behavior of multithreaded object-oriented applications in multicores
inferred← citeshttps://doi.org/10.1109/iccd.2007.4601934openalex-snapshot
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation
inferred← citeshttps://doi.org/10.1109/iccd.2011.6081367openalex-snapshot
Memory coherence in the age of multicores
inferred← citeshttps://doi.org/10.1109/iccd.2011.6081371openalex-snapshot
Leveraging torus topology with deadlock recovery for cost-efficient on-chip network
inferred← citeshttps://doi.org/10.1109/iccd.2013.6657040openalex-snapshot
Scattered superpage: A case for bridging the gap between superpage and page coloring
inferred← citeshttps://doi.org/10.1109/iccd.2017.32openalex-snapshot
CAGE: A Contention-Aware Game-Theoretic Model for Heterogeneous Resource Assignment
inferred← citeshttps://doi.org/10.1109/iccd.2017.97openalex-snapshot
CloudShelter: Protecting Virtual Machines' Memory Resource Availability in Clouds
inferred← citeshttps://doi.org/10.1109/iccet.2010.5485345openalex-snapshot
Event-based analysis of a L2 prefetch related parallel nonscaling on intel dual core processor
inferred← citeshttps://doi.org/10.1109/icde.2018.00047openalex-snapshot
Accelerating Concurrent Workloads with CPU Cache Partitioning
inferred← citeshttps://doi.org/10.1109/icpads.2015.98openalex-snapshot
Contention-Aware Scheduling for Asymmetric Multicore Processors
inferred← citeshttps://doi.org/10.1109/icpp.2008.29openalex-snapshot
Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches
inferred← citeshttps://doi.org/10.1109/icpp.2008.7openalex-snapshot
TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation
inferred← citeshttps://doi.org/10.1109/icpp.2011.59openalex-snapshot
Understanding Off-Chip Memory Contention of Parallel Programs in Multicore Systems
inferred← citeshttps://doi.org/10.1109/icpp.2011.72openalex-snapshot
Symbiotic Scheduling for Shared Caches in Multi-core Systems Using Memory Footprint Signature
inferred← citeshttps://doi.org/10.1109/icpp.2012.8openalex-snapshot
A Flexible Framework for Throttling-Enabled Multicore Management (TEMM)
inferred← citeshttps://doi.org/10.1109/icpp.2013.70openalex-snapshot
Temporal-Aware Mechanism to Detect Private Data in Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/icspcc.2012.6335721openalex-snapshot
A survey on cache coherence for tiled many-core processor
inferred← citeshttps://doi.org/10.1109/ims3tw.2014.6997403openalex-snapshot
Integrated cross-layer solutions for enabling silicon photonics into future chip multiprocessors
inferred← citeshttps://doi.org/10.1109/ipdps.2012.121openalex-snapshot
FractalMRC: Online Cache Miss Rate Curve Prediction on Commodity Systems
inferred← citeshttps://doi.org/10.1109/ipdps.2016.26openalex-snapshot
TintMalloc: Reducing Memory Access Divergence via Controller-Aware Coloring
inferred← citeshttps://doi.org/10.1109/ipdps47924.2020.00066openalex-snapshot
DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/ipdpsw.2010.5470753openalex-snapshot
A reconfigurable architecture for multicore systems
inferred← citeshttps://doi.org/10.1109/ipdpsw.2012.31openalex-snapshot
A Heterogeneous Cache Distribution with Reconfigurable Interconnect
inferred← citeshttps://doi.org/10.1109/isca.2014.6853214openalex-snapshot
Going vertical in memory management: Handling multiplicity by multi-policy
inferred← citeshttps://doi.org/10.1109/islped.2011.5993647openalex-snapshot
A design space exploration of transmission-line links for on-chip interconnect
inferred← citeshttps://doi.org/10.1109/ispa.2009.22openalex-snapshot
Data Management: The Spirit to Pursuit Peak Performance on Many-Core Processor
inferred← citeshttps://doi.org/10.1109/ispa.2009.47openalex-snapshot
A Simple Cache Partitioning Approach in a Virtualized Environment
inferred← citeshttps://doi.org/10.1109/isqed.2015.7085472openalex-snapshot
Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networks
inferred← citeshttps://doi.org/10.1109/issa.2014.6950494openalex-snapshot
On a domain block based mechanism to mitigate DoS attacks on shared caches in asymmetric multiprocessing multi operating systems
inferred← citeshttps://doi.org/10.1109/jetcas.2012.2193519openalex-snapshot
Using Transmission Lines for Global On-Chip Communication
inferred← citeshttps://doi.org/10.1109/jsyst.2015.2430522openalex-snapshot
Coordinate Channel-Aware Page Mapping Policy and Memory Scheduling for Reducing Memory Interference Among Multimedia Applications
inferred← citeshttps://doi.org/10.1109/l-ca.2007.10openalex-snapshot
Flattened Butterfly Topology for On-Chip Networks
inferred← citeshttps://doi.org/10.1109/l-ca.2011.18openalex-snapshot
Experience with Improving Distributed Shared Cache Performance on Tilera's Tile Processor
inferred← citeshttps://doi.org/10.1109/mascots.2018.00022openalex-snapshot
Quantifying and Optimizing Data Access Parallelism on Manycores
inferred← citeshttps://doi.org/10.1109/micro.2007.15openalex-snapshot
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
inferred← citeshttps://doi.org/10.1109/micro.2007.17openalex-snapshot
A Framework for Providing Quality of Service in Chip Multi-Processors
inferred← citeshttps://doi.org/10.1109/micro.2007.29openalex-snapshot
Flattened Butterfly Topology for On-Chip Networks
inferred← citeshttps://doi.org/10.1109/micro.2008.4771796openalex-snapshot
Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer
inferred← citeshttps://doi.org/10.1109/micro.2012.40openalex-snapshot
Predicting Coherence Communication by Tracking Synchronization Points at Run Time
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00061openalex-snapshot
Jumanji: The Case for Dynamic NUCA in the Datacenter
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00120openalex-snapshot
Stream-Based Data Placement for Near-Data Processing with Extended Memory
inferred← citeshttps://doi.org/10.1109/mm.2010.22openalex-snapshot
Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures
inferred← citeshttps://doi.org/10.1109/nas.2010.25openalex-snapshot
Fast Hierarchical Cache Directory: A Scalable Cache Organization for Large-Scale CMP
inferred← citeshttps://doi.org/10.1109/nas.2012.27openalex-snapshot
PSA-NUCA: A Pressure Self-Adapting Dynamic Non-uniform Cache Architecture
inferred← citeshttps://doi.org/10.1109/nas.2014.44openalex-snapshot
Archipelago: A Floorplan Optimized for Concurrent Multiple Applications on Network-on-Chip
inferred← citeshttps://doi.org/10.1109/nca.2011.37openalex-snapshot
NoC Reconfiguration for CMP Virtualization
inferred← citeshttps://doi.org/10.1109/netsoft48620.2020.9165471openalex-snapshot
RLDRM: Closed Loop Dynamic Cache Allocation with Deep Reinforcement Learning for Network Function Virtualization
inferred← citeshttps://doi.org/10.1109/nocs.2013.6558410openalex-snapshot
An NoC and cache hierarchy substrate to address effective virtualization and fault-tolerance
inferred← citeshttps://doi.org/10.1109/pact.2009.14openalex-snapshot
SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/pact.2009.35openalex-snapshot
Soft-OLP: Improving Hardware Cache Performance through Software-Controlled Object-Level Partitioning
inferred← citeshttps://doi.org/10.1109/pact.2013.6618817openalex-snapshot
The case for a scalable coherence protocol for complex on-chip cache hierarchies in many core systems
inferred← citeshttps://doi.org/10.1109/pact.2013.6618818openalex-snapshot
Meeting midway: improving CMP performance with memory-side prefetching
inferred← citeshttps://doi.org/10.1109/pact.2017.42openalex-snapshot
Nexus: A New Approach to Replication in Distributed Shared Caches
inferred← citeshttps://doi.org/10.1109/padsw.2014.7097821openalex-snapshot
Combine thread with memory scheduling for maximizing performance in multi-core systems
inferred← citeshttps://doi.org/10.1109/pdp.2012.47openalex-snapshot
Exploring NoC Virtualization Alternatives in CMPs
inferred← citeshttps://doi.org/10.1109/rtcsa.2007.16openalex-snapshot
Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems
inferred← citeshttps://doi.org/10.1109/rtcsa.2014.6910521openalex-snapshot
PUMA: Pseudo unified memory architecture for single-ISA heterogeneous multi-core systems
inferred← citeshttps://doi.org/10.1109/rtss.2016.026openalex-snapshot
MARACAS: A Real-Time Multicore VCPU Scheduling Framework
inferred← citeshttps://doi.org/10.1109/samos.2014.6893201openalex-snapshot
Extended performance analysis of the time predictable on-demand coherent data cache for multi- and many-core systems
inferred← citeshttps://doi.org/10.1109/sbac-pad.2010.20openalex-snapshot
Feedback-Driven Restructuring of Multi-threaded Applications for NUCA Cache Performance in CMPs
inferred← citeshttps://doi.org/10.1109/sbac-pad.2015.21openalex-snapshot
Unifying Router Power Gating with Data Placement for Energy-Efficient NoC
inferred← citeshttps://doi.org/10.1109/sbac-padw.2015.19openalex-snapshot
On the Evaluation of Contention-Aware List Schedulers on Multicore Cluster
inferred← citeshttps://doi.org/10.1109/sbesc.2014.8openalex-snapshot
On the Influence of Shared Memory Contention in Real-Time Multicore Applications
inferred← citeshttps://doi.org/10.1109/sc.2008.5216918openalex-snapshot
A novel migration-based NUCA design for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/sc.2010.35openalex-snapshot
On-Chip Network Evaluation Framework
inferred← citeshttps://doi.org/10.1109/sc.2010.50openalex-snapshot
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support
inferred← citeshttps://doi.org/10.1109/sc.2012.81openalex-snapshot
NUMA-aware graph mining techniques for performance and energy efficiency
inferred← citeshttps://doi.org/10.1109/sc41404.2022.00085openalex-snapshot
TD-NUCA: Runtime Driven Management of NUCA Caches in Task Dataflow Programming Models
inferred← citeshttps://doi.org/10.1109/sc41406.2024.00017openalex-snapshot
Hydrogen: Contention-Aware Hybrid Memory for Heterogeneous CPU-GPU Architectures
inferred← citeshttps://doi.org/10.1109/scc.2013.116openalex-snapshot
Variations in Performance Measurements of Multi-core Processors: A Study of n-Tier Applications
inferred← citeshttps://doi.org/10.1109/sp.2015.42openalex-snapshot
S$A: A Shared Cache Attack That Works across Cores and Defies VM Sandboxing -- and Its Application to AES
inferred← citeshttps://doi.org/10.1109/tc.2009.138openalex-snapshot
PERFECTORY: A Fault-Tolerant Directory Memory Architecture
inferred← citeshttps://doi.org/10.1109/tc.2012.129openalex-snapshot
Process Variation-Aware Nonuniform Cache Management in a 3D Die-Stacked Multicore Processor
inferred← citeshttps://doi.org/10.1109/tc.2015.2462813openalex-snapshot
Rethinking Memory Management in Modern Operating System: Horizontal, Vertical or Random?
inferred← citeshttps://doi.org/10.1109/tcad.2016.2582872openalex-snapshot
Achieving Versatile and Simultaneous Cache Optimizations With Nonvolatile SRAM
inferred← citeshttps://doi.org/10.1109/tpds.2011.238openalex-snapshot
Codesign of NoC and Cache Organization for Reducing Access Latency in Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/tpds.2015.2412139openalex-snapshot
Efficient TLB-Based Detection of Private Pages in Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/tpds.2015.2442983openalex-snapshot
Predicting Cross-Core Performance Interference on Multicore Processors with Regression Analysis
inferred← citeshttps://doi.org/10.1109/tpds.2017.2657512openalex-snapshot
Dynamic Associativity Management in Tiled CMPs by Runtime Adaptation of Fellow Sets
inferred← citeshttps://doi.org/10.1109/tpds.2017.2713778openalex-snapshot
A Hardware Approach to Fairly Balance the Inter-Thread Interference in Shared Caches
inferred← citeshttps://doi.org/10.1109/tvlsi.2011.2158249openalex-snapshot
LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors
inferred← citeshttps://doi.org/10.1109/tvlsi.2016.2642587openalex-snapshot
Fighting Dark Silicon: Toward Realizing Efficient Thermal-Aware 3-D Stacked Multiprocessors
inferred← citeshttps://doi.org/10.1109/tvlsi.2021.3135502openalex-snapshot
Taming Process Variations in CNFET for Efficient Last-Level Cache Design
inferred← citeshttps://doi.org/10.1109/vlsisoc.2010.5642686openalex-snapshot
Temperature- and bus traffic- aware data placement in 3D-stacked cache
inferred← citeshttps://doi.org/10.1145/1150019.1136509openalex-snapshot
Cooperative Caching for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1145/1250662.1250670openalex-snapshot
Virtual hierarchies to support server consolidation
inferred← citeshttps://doi.org/10.1145/1273440.1250670openalex-snapshot
Virtual hierarchies to support server consolidation
inferred← citeshttps://doi.org/10.1145/1519065.1519076openalex-snapshot
Towards practical page coloring-based multicore cache management
inferred← citeshttps://doi.org/10.1145/1531793.1531803openalex-snapshot
Enhancing operating system support for multicore processors by using hardware performance monitoring
inferred← citeshttps://doi.org/10.1145/1542275.1542289openalex-snapshot
Dynamic cache clustering for chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1555754.1555781openalex-snapshot
A case for bufferless routing in on-chip networks
inferred← citeshttps://doi.org/10.1145/1555815.1555781openalex-snapshot
A case for bufferless routing in on-chip networks
inferred← citeshttps://doi.org/10.1145/1654059.1654074openalex-snapshot
Enabling software management for multicore caches with a lightweight hardware support
inferred← citeshttps://doi.org/10.1145/1669112.1669141openalex-snapshot
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
inferred← citeshttps://doi.org/10.1145/1735970.1736036openalex-snapshot
Addressing shared resource contention in multicore processors via scheduling
inferred← citeshttps://doi.org/10.1145/1735971.1736036openalex-snapshot
Addressing shared resource contention in multicore processors via scheduling
inferred← citeshttps://doi.org/10.1145/1736020.1736036openalex-snapshot
Addressing shared resource contention in multicore processors via scheduling
inferred← citeshttps://doi.org/10.1145/1854273.1854284openalex-snapshot
Dynamically managed multithreaded reconfigurable architectures for chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1854273.1854314openalex-snapshot
Handling the problems and opportunities posed by multiple on-chip memory controllers
inferred← citeshttps://doi.org/10.1145/1854273.1854353openalex-snapshot
Online cache modeling for commodity multicore processors
inferred← citeshttps://doi.org/10.1145/1880018.1880019openalex-snapshot
Contention-Aware Scheduling on Multicore Systems
inferred← citeshttps://doi.org/10.1145/1880037.1880039openalex-snapshot
Quality of service shared cache management in chip multiprocessor architecture
inferred← citeshttps://doi.org/10.1145/1882453.1882455openalex-snapshot
Power and performance aware reconfigurable cache for CMPs
inferred← citeshttps://doi.org/10.1145/1899928.1899931openalex-snapshot
Online cache modeling for commodity multicore processors
inferred← citeshttps://doi.org/10.1145/1944862.1944887openalex-snapshot
Directly characterizing cross core interference through contention synthesis
inferred← citeshttps://doi.org/10.1145/1995896.1995942openalex-snapshot
Controlling cache utilization of HPC applications
inferred← citeshttps://doi.org/10.1145/2000064.2000097openalex-snapshot
A case for globally shared-medium on-chip interconnect
inferred← citeshttps://doi.org/10.1145/2000417.2000419openalex-snapshot
Contentiousness vs. sensitivity
inferred← citeshttps://doi.org/10.1145/2024723.2000097openalex-snapshot
A case for globally shared-medium on-chip interconnect
inferred← citeshttps://doi.org/10.1145/2155620.2155677openalex-snapshot
A data layout optimization framework for NUCA-based multicores
inferred← citeshttps://doi.org/10.1145/2245276.2232065openalex-snapshot
Reducing last level cache pollution through OS-level software-controlled region-based partitioning
showing the first 200 of 295 · page through all 295
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