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Adaptive History-Based Memory Schedulers
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-0-387-09766-4_133openalex-snapshot
NAS Parallel Benchmarks
inferredcites →https://doi.org/10.1109/12.895941openalex-snapshot
Dynamic access ordering for streamed computations
inferredcites →https://doi.org/10.1109/40.918001openalex-snapshot
Imagine: media processing with streams
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Impulse: building a smarter memory controller
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Increasing the Number of Strides for Conflict-free Vector Access
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IBM power5 chip: a dual-core multithreaded processor
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Performance Optimizations and Bounds for Sparse Matrix-Vector Multiply
inferredcites →https://doi.org/10.1145/139669.140400openalex-snapshot
Increasing the number of strides for conflict-free vector access
inferredcites →https://doi.org/10.1145/237090.237144openalex-snapshot
Synchronization and communication in the T3E multiprocessor
inferredcites →https://doi.org/10.1145/335231.335247openalex-snapshot
Hardware-only stream prefetching and dynamic access ordering
inferredcites →https://doi.org/10.1145/859618.859643openalex-snapshot
Performance analysis of the Alpha 21364-based HP GS1280 multiprocessor
inferredcites →https://doi.org/10.1145/996566.996749openalex-snapshot
Design and implementation of the POWER5™ microprocessor
inferredcites →https://doi.org/10.1177/109434209100500306openalex-snapshot
The NAS Parallel Benchmarks
inferredcites →https://doi.org/10.18130/v37n35openalex-snapshot
Access Ordering and Effective Memory Bandwidth
inferredcites →https://doi.org/10.5555/762761.762822openalex-snapshot
Performance Optimizations and Bounds for Sparse Matrix-Vector Multiply
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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OS Scheduling Algorithms for Improving the Performance of Multithreaded Workloads
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Prediction in Dynamic SDRAM Controller Policies
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Software-Hardware Cooperative DRAM Bank Partitioning for Chip Multiprocessors
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Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy
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PARBLO: Page-Allocation-Based DRAM Row Buffer Locality Optimization
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Memory access schedule minimization for embedded systems
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DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
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A Highly Parallel DRAM Architecture to Mitigate Large Access Latency and Improve Energy Efficiency of Modern DRAM Systems
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Fair-Priority-Expression-Based burst scheduling to enhance performance and fairness of shared dram systems
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A quantitative analysis of performance benefits of 3D die stacking on mobile and embedded SoC
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A comprehensive approach to DRAM power management
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Power-Efficient DRAM Speculation
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ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers
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MORSE: Multi-objective reconfigurable self-optimizing memory scheduler
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Improving system throughput and fairness simultaneously in shared memory CMP systems via Dynamic Bank Partitioning
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DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators
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AsyncDIMM: Achieving Asynchronous Execution in DIMM-Based Near-Memory Processing
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The Virtual Open Page Buffer for Multi-core and Multi-thread Processors
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Low-cost open-page prefetch scheduling in chip multiprocessors
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Energy efficient DRAM row buffer management for enterprise workloads
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Memory Access Scheduling Schemes for Systems with Multi-Core Processors
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A priority-expression-based burst scheduling of memory reordering access
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Core-aware memory access scheduling schemes
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An Analytical Performance Model for Partitioning Off-Chip Memory Bandwidth
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Self-Adaptive Address Mapping Mechanism for Access Pattern Awareness on DRAM
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Automatic testcase synthesis and performance model validation for highperformance PowerPC processors
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Agent-Based Memory Access for Many-Core CMPs
inferred← citeshttps://doi.org/10.1109/mcsoc.2014.50openalex-snapshot
Time-Based Least Memory Intensive Scheduling
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Adaptive Time-Based Least Memory Intensive Scheduling
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Memory Prefetching Using Adaptive Stream Detection
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Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors
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Process Variation Tolerant 3T1D-Based Cache Architectures
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Prefetch-Aware DRAM Controllers
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Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs
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Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
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Improving bank-level parallelism for irregular applications
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FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching
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A novel scheduling algorithm for phase change memory based main memory system with multiple ranks
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Adaptive History-Based Memory Schedulers for Modern Processors
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Effective Management of DRAM Bandwidth in Multicore Processors
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Memory Architecture for Integrating Emerging Memory Technologies
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Combine thread with memory scheduling for maximizing performance in multi-core systems
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HiTS: A High Throughput Memory Scheduling Scheme to Mitigate Denial-of-Service Attacks in Multi-core Systems
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Power and Performance Trade-Offs in Contemporary DRAM System Designs for Multicore Processors
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Prefetch-Aware Memory Controllers
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Thread Row Buffers: Improving Memory Performance Isolation and Throughput in Multiprogrammed Environments
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Low-Overhead Network-on-Chip Support for Location-Oblivious Task Placement
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Real-Time Scheduling for Phase Change Main Memory Systems
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Intelligent Architectures for Intelligent Machines
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The bit-reversal SDRAM address mapping
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Thermal modeling and management of DRAM memory systems
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Memory scheduling for modern microprocessors
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Optimizing thread throughput for multithreaded workloads on memory constrained CMPs
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Parallelism-Aware Batch Scheduling
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3D-Stacked Memory Architectures for Multi-core Processors
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Self-Optimizing Memory Controllers
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FPGA implementation & comparison of current trends in memory scheduler for multimedia application
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A bursty multi-port memory controller with quality-of-service guarantees
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Parallel application memory scheduling
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Reducing memory interference in multicore systems via application-aware memory channel partitioning
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Rank idle time prediction driven last-level cache writeback
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DRAM power-aware rank scheduling
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Survey of scheduling techniques for addressing shared resources in multicore processors
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A network congestion-aware memory subsystem for manycore
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Reducing DRAM row activations with eager read/write clustering
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System-Level Performance and Power Optimization for MPSoC
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Memory Access Scheduling Based on Dynamic Multilevel Priority in Shared DRAM Systems
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Providing Predictable Performance via a Slowdown Estimation Model
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Using Criticality of GPU Accesses in Memory Management for CPU-GPU Heterogeneous Multi-Core Processors
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Demystifying Complex Workload-DRAM Interactions
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Co-optimizing memory-level parallelism and cache-level parallelism
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Efficient Generation of Application Specific Memory Controllers
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DX100: Programmable Data Access Accelerator for Indirection
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A Mathematical Model for XOR-Based Application Specific DRAM Address Mapping Schemes
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Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
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Reducing On-Chip DRAM Energy via Data Transfer Size Optimization
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Intelligent Architectures for Intelligent Computing Systems
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Reducing main memory access latency through SDRAM address mapping techniques and access reordering mechanisms
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DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
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Understanding the Interactions of Workloads and DRAM Types: A Comprehensive Experimental Study
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Improving bank-level parallelism for irregular applications
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Adaptive memory hierarchies for next generation tiled microarchitectures
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Work-conserving dynamic TDM-based memory arbitration for multi-criticality real-time systems
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Hardware-Accelerated Range Partitioning
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