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Merging Head and Tail Duplication for Convergent Hyperblock Formation
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/spe.4380211204openalex-snapshot
Using profile information to assist classic code optimizations
inferredcites →https://doi.org/10.1007/978-3-540-71528-3_10openalex-snapshot
Convergent Compilation Applied to Loop Unrolling
inferredcites →https://doi.org/10.1007/bf01205185openalex-snapshot
The superblock: An effective technique for VLIW and superscalar compilation
inferredcites →https://doi.org/10.1023/a:1018787007582openalex-snapshot
The Partial Reverse If-Conversion Framework for Balancing Control Flow and Predication
inferredcites →https://doi.org/10.1109/71.476167openalex-snapshot
Resource-constrained software pipelining
inferredcites →https://doi.org/10.1109/hpca.1998.650566openalex-snapshot
Treegion scheduling for wide issue processors
inferredcites →https://doi.org/10.1109/l-ca.2002.8openalex-snapshot
MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research
inferredcites →https://doi.org/10.1109/mc.2004.65openalex-snapshot
Scaling to the end of silicon with EDGE architectures
inferredcites →https://doi.org/10.1109/micro.1992.696999openalex-snapshot
Effective Compiler Support For Predicated Execution Using The Hyperblock
inferredcites →https://doi.org/10.1109/micro.1996.566451openalex-snapshot
Speculative hedge: regulating compile-time speculation against profile variations
inferredcites →https://doi.org/10.1109/micro.1996.566461openalex-snapshot
Increasing the instruction fetch rate via block-structured instruction set architectures
inferredcites →https://doi.org/10.1109/pact.2004.1342543openalex-snapshot
Static placement, dynamic issue (SPDI) scheduling for EDGE architectures
inferredcites →https://doi.org/10.1109/tc.1981.1675827openalex-snapshot
Trace Scheduling: A Technique for Global Microcode Compaction
inferredcites →https://doi.org/10.1145/1096419.1096424openalex-snapshot
Tree compaction of microprograms
inferredcites →https://doi.org/10.1145/1168857.1168875openalex-snapshot
A spatial path scheduling algorithm for EDGE architectures
inferredcites →https://doi.org/10.1145/144965.144998openalex-snapshot
Effective compiler support for predicated execution using the hyperblock
inferredcites →https://doi.org/10.1145/53990.54022openalex-snapshot
Software pipelining: an effective scheduling technique for VLIW machines
inferredcites →https://doi.org/10.1145/567067.567085openalex-snapshot
Conversion of control dependence to data dependence
inferredcites →https://doi.org/10.5555/1025127.1025998openalex-snapshot
Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures
inferredcites →https://doi.org/10.5555/243846.243859openalex-snapshot
Speculative hedge: regulating compile-time speculation against profile variations
inferredcites →https://doi.org/10.5555/243846.243885openalex-snapshot
Increasing the instruction fetch rate via block-structured instruction set architectures
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-1-4419-0263-4_3openalex-snapshot
Composable Multicore Chips
inferred← citeshttps://doi.org/10.1007/978-3-540-71528-3_10openalex-snapshot
Convergent Compilation Applied to Loop Unrolling
inferred← citeshttps://doi.org/10.1007/978-3-540-89740-8_5openalex-snapshot
Register Bank Assignment for Spatially Partitioned Processors
inferred← citeshttps://doi.org/10.1007/s10766-014-0320-yopenalex-snapshot
pocl: A Performance-Portable OpenCL Implementation
inferred← citeshttps://doi.org/10.1109/elinfocom.2014.6914376openalex-snapshot
Performance evaluation of GCC 4.7.1 on EISC
inferred← citeshttps://doi.org/10.1109/iccd.2010.5647735openalex-snapshot
M5 based EDGE architecture modeling
inferred← citeshttps://doi.org/10.1109/interact.2011.17openalex-snapshot
The Good Block: Hardware/Software Design for Composable, Block-Atomic Processors
inferred← citeshttps://doi.org/10.1109/ispass.2009.4919651openalex-snapshot
Analysis of the TRIPS prototype block predictor
inferred← citeshttps://doi.org/10.1145/1454115.1454122openalex-snapshot
Feature selection and policy optimization for distributed instruction placement using reinforcement learning
inferred← citeshttps://doi.org/10.1145/1508244.1508246openalex-snapshot
An evaluation of the TRIPS computer system
inferred← citeshttps://doi.org/10.1145/1508284.1508246openalex-snapshot
An evaluation of the TRIPS computer system
inferred← citeshttps://doi.org/10.1145/2528521.1508246openalex-snapshot
An evaluation of the TRIPS computer system
inferred← citeshttps://doi.org/10.1609/aaai.v24i1.7711openalex-snapshot
Evolving Compiler Heuristics to Manage Communication and Contention
inferred← citeshttps://doi.org/10.47749/t/unicamp.2011.782478openalex-snapshot
Técnicas e arquitetura para captura de traços e execução especulativa
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