On the public citation graph

Dataflow Predication

https://doi.org/10.1109/micro.2006.17
0 signed · 62 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/bf01205182openalex-snapshot
The multiflow trace scheduling compiler
inferredcites →https://doi.org/10.1016/0743-7315(91)90016-3openalex-snapshot
From control flow to dataflow
inferredcites →https://doi.org/10.1109/12.48862openalex-snapshot
Executing a program on the MIT tagged-token dataflow architecture
inferredcites →https://doi.org/10.1109/2.19820openalex-snapshot
The Cydra 5 departmental supercomputer: design philosophies, decisions, and trade-offs
inferredcites →https://doi.org/10.1109/40.755465openalex-snapshot
The Alpha 21264 microprocessor
inferredcites →https://doi.org/10.1109/cgo.2006.10openalex-snapshot
Compiling for EDGE Architectures
inferredcites →https://doi.org/10.1109/hicss.1993.283949openalex-snapshot
The benefit of predicated execution for software pipelining
inferredcites →https://doi.org/10.1109/hpca.2001.903248openalex-snapshot
Register renaming and scheduling for dynamic execution of predicated code
inferredcites →https://doi.org/10.1109/isca.1994.288156openalex-snapshot
Guarded execution and branch prediction in dynamic ILP processors
inferredcites →https://doi.org/10.1109/isca.1999.765952openalex-snapshot
The program decision logic approach to predicated execution
inferredcites →https://doi.org/10.1109/mc.2004.65openalex-snapshot
Scaling to the end of silicon with EDGE architectures
inferredcites →https://doi.org/10.1109/micro.1992.696999openalex-snapshot
Effective Compiler Support For Predicated Execution Using The Hyperblock
inferredcites →https://doi.org/10.1109/micro.1997.645801openalex-snapshot
A framework for balancing control flow and predication
inferredcites →https://doi.org/10.1109/micro.2003.1253203openalex-snapshot
WaveScalar
inferredcites →https://doi.org/10.1109/micro.2005.38openalex-snapshot
Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution
inferredcites →https://doi.org/10.1109/micro.2006.34openalex-snapshot
Merging Head and Tail Duplication for Convergent Hyperblock Formation
inferredcites →https://doi.org/10.1145/1024393.1024396openalex-snapshot
Spatial computation
inferredcites →https://doi.org/10.1145/115372.115320openalex-snapshot
Efficiently computing static single assignment form and the control dependence graph
inferredcites →https://doi.org/10.1145/1168857.1168875openalex-snapshot
A spatial path scheduling algorithm for EDGE architectures
inferredcites →https://doi.org/10.1145/143365.143529openalex-snapshot
Sentinel scheduling for VLIW and superscalar processors
inferredcites →https://doi.org/10.1145/144965.144998openalex-snapshot
Effective compiler support for predicated execution using the hyperblock
inferredcites →https://doi.org/10.1145/191995.192022openalex-snapshot
Guarded execution and branch prediction in dynamic ILP processors
inferredcites →https://doi.org/10.1145/285930.286058openalex-snapshot
A preliminary architecture for a basic data-flow processor
inferredcites →https://doi.org/10.1145/300979.300997openalex-snapshot
The program decision logic approach to predicated execution
inferredcites →https://doi.org/10.1145/359327.359336openalex-snapshot
The CRAY-1 computer system
inferredcites →https://doi.org/10.1145/567067.567085openalex-snapshot
Conversion of control dependence to data dependence
inferredcites →https://doi.org/10.1145/642089.642111openalex-snapshot
A preliminary architecture for a basic data-flow processor
inferredcites →https://doi.org/10.1145/68182.68185openalex-snapshot
Overlapped loop support in the Cydra 5
inferredcites →https://doi.org/10.1145/70082.68185openalex-snapshot
Overlapped loop support in the Cydra 5
inferredcites →https://doi.org/10.1145/782814.782840openalex-snapshot
Predicate prediction for efficient out-of-order execution
inferredcites →https://doi.org/10.5555/266800.266810openalex-snapshot
A framework for balancing control flow and predication

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-1-4419-0263-4_3openalex-snapshot
Composable Multicore Chips
inferred← citeshttps://doi.org/10.1007/978-1-4614-4992-8_7openalex-snapshot
Front-End Design Flow: Bridging the Algorithm-Architecture Gap
inferred← citeshttps://doi.org/10.1007/978-3-540-92990-1_24openalex-snapshot
Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures
inferred← citeshttps://doi.org/10.1016/j.cola.2021.101052openalex-snapshot
Program diagramming and fundamental programming patterns for a polymorphic computing dataflow processor
inferred← citeshttps://doi.org/10.1109/apcsac.2008.4625471openalex-snapshot
Profile guided optimization for dataflow predication
inferred← citeshttps://doi.org/10.1109/hpca.2009.4798255openalex-snapshot
Lightweight predication support for out of order processors
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00063openalex-snapshot
A Hybrid Systolic-Dataflow Architecture for Inductive Matrix Algorithms
inferred← citeshttps://doi.org/10.1109/iccda.2010.5541503openalex-snapshot
A novel mutli-cores MCU architecture based on data flow computing
inferred← citeshttps://doi.org/10.1109/interact.2011.17openalex-snapshot
The Good Block: Hardware/Software Design for Composable, Block-Atomic Processors
inferred← citeshttps://doi.org/10.1109/isca.2014.6853234openalex-snapshot
Single-graph multiple flows: Energy efficient design alternative for GPGPUs
inferred← citeshttps://doi.org/10.1109/iscas45731.2020.9181277openalex-snapshot
Fine-Grained Instruction Placement in Polymorphic Computing Architectures
inferred← citeshttps://doi.org/10.1109/micro.2006.34openalex-snapshot
Merging Head and Tail Duplication for Convergent Hyperblock Formation
inferred← citeshttps://doi.org/10.1109/mm.2014.14openalex-snapshot
Efficient Spatial Processing Element Control via Triggered Instructions
inferred← citeshttps://doi.org/10.1109/mocast49295.2020.9200304openalex-snapshot
Issue-Slot Based Predication Encoding Technique for VLIW Processors
inferred← citeshttps://doi.org/10.1109/soccon.2009.5398055openalex-snapshot
JavaFlow — A Java dataflow machine
inferred← citeshttps://doi.org/10.1109/tpds.2018.2819670openalex-snapshot
A Dataflow Processor as the Basis of a Tiled Polymorphic Computing Architecture with Fine-Grain Instruction Migration
inferred← citeshttps://doi.org/10.1145/1250662.1250717openalex-snapshot
Transparent control independence (TCI)
inferred← citeshttps://doi.org/10.1145/1508244.1508246openalex-snapshot
An evaluation of the TRIPS computer system
inferred← citeshttps://doi.org/10.1145/1508284.1508246openalex-snapshot
An evaluation of the TRIPS computer system
inferred← citeshttps://doi.org/10.1145/1854273.1854327openalex-snapshot
The potential of using dynamic information flow analysis in data value prediction
inferred← citeshttps://doi.org/10.1145/1926367.1926379openalex-snapshot
Software-based branch predication for AMD GPUs
inferred← citeshttps://doi.org/10.1145/2133382.2133383openalex-snapshot
Leveraging Strength-Based Dynamic Information Flow Analysis to Enhance Data Value Prediction
inferred← citeshttps://doi.org/10.1145/2304576.2304580openalex-snapshot
Distributed replay protocol for distributed uniprocessors
inferred← citeshttps://doi.org/10.1145/2528521.1508246openalex-snapshot
An evaluation of the TRIPS computer system
inferred← citeshttps://doi.org/10.1145/2678373.2665703openalex-snapshot
Single-graph multiple flows
inferred← citeshttps://doi.org/10.1145/2749469.2750390openalex-snapshot
Efficient execution of memory access phases using dataflow specialization
inferred← citeshttps://doi.org/10.1145/2754930openalex-snapshot
Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures
inferred← citeshttps://doi.org/10.1145/3007902openalex-snapshot
Performance Scalability of Adaptive Processor Architecture
inferred← citeshttps://doi.org/10.1145/3760436openalex-snapshot
The TRIPS Project
inferred← citeshttps://doi.org/10.14529/jsfi140102openalex-snapshot
Runtime-Aware Architectures: A First Approach
inferred← citeshttps://doi.org/10.7916/d88p67dzopenalex-snapshot
Rapid Parallelization by Collaboration
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.