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Architectural Support for Software Transactional Memory
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11561927_26openalex-snapshot
Adaptive Software Transactional Memory
inferredcites →https://doi.org/10.1016/j.scico.2006.05.010openalex-snapshot
Nested transactional memory: Model and architecture sketches
inferredcites →https://doi.org/10.1109/hotchips.2006.7477739openalex-snapshot
Software transactional memory
inferredcites →https://doi.org/10.1109/hpca.1998.650559openalex-snapshot
Speculative versioning cache
inferredcites →https://doi.org/10.1109/hpca.2006.1598134openalex-snapshot
LogTM: Log-based Transactional Memory
inferredcites →https://doi.org/10.1109/hpca.2006.1598135openalex-snapshot
The Common Case Transactional Behavior of Multithreaded Programs
inferredcites →https://doi.org/10.1109/isca.1993.698569openalex-snapshot
Transactional Memory: Architectural Support For Lock-free Data Structures
inferredcites →https://doi.org/10.1109/isca.2005.54openalex-snapshot
Virtualizing Transactional Memory
inferredcites →https://doi.org/10.1109/isca.2006.9openalex-snapshot
Architectural Semantics for Practical Transactional Memory
inferredcites →https://doi.org/10.1145/1024393.1024395openalex-snapshot
Programming with transactional coherence and consistency (TCC)
inferredcites →https://doi.org/10.1145/1065944.1065952openalex-snapshot
Composable memory transactions
inferredcites →https://doi.org/10.1145/1073814.1073861openalex-snapshot
Advanced contention management for dynamic software transactional memory
inferredcites →https://doi.org/10.1145/1080695.1070011openalex-snapshot
Virtualizing Transactional Memory
inferredcites →https://doi.org/10.1145/1133255.1133984openalex-snapshot
Optimizing memory transactions
inferredcites →https://doi.org/10.1145/1133255.1133985openalex-snapshot
Compiler and runtime support for efficient software transactional memory
inferredcites →https://doi.org/10.1145/1133981.1133983openalex-snapshot
The Atomos transactional programming language
inferredcites →https://doi.org/10.1145/1133981.1133984openalex-snapshot
Optimizing memory transactions
inferredcites →https://doi.org/10.1145/1133981.1133985openalex-snapshot
Compiler and runtime support for efficient software transactional memory
inferredcites →https://doi.org/10.1145/1150019.1136491openalex-snapshot
Architectural Semantics for Practical Transactional Memory
inferredcites →https://doi.org/10.1145/1168857.1168902openalex-snapshot
Supporting nested transactional memory in logTM
inferredcites →https://doi.org/10.1145/2641638.2641654openalex-snapshot
Language support for lightweight transactions
inferredcites →https://doi.org/10.1145/605397.605399openalex-snapshot
Transactional lock-free execution of lock-based programs
inferredcites →https://doi.org/10.1145/872035.872048openalex-snapshot
Software transactional memory for dynamic-sized data structures
inferredcites →https://doi.org/10.1145/949305.949340openalex-snapshot
Language support for lightweight transactions
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cpe.1336openalex-snapshot
Compiler and runtime techniques for software transactional memory optimization
inferred← citeshttps://doi.org/10.1007/978-1-4419-0263-4_5openalex-snapshot
Optimizing Memory Transactions for Multicore Systems
inferred← citeshttps://doi.org/10.1007/978-3-031-01740-7openalex-snapshot
Shared-Memory Synchronization
inferred← citeshttps://doi.org/10.1007/978-3-319-11194-0_19openalex-snapshot
Improving Speculation Accuracy with Inter-thread Fetching Value Prediction
inferred← citeshttps://doi.org/10.1007/978-3-540-69303-1_4openalex-snapshot
Transactional Memory and OpenMP
inferred← citeshttps://doi.org/10.1007/978-3-642-03644-6_6openalex-snapshot
SPMTM: A Novel ScratchPad Memory Based Hybrid Nested Transactional Memory Framework
inferred← citeshttps://doi.org/10.1007/978-3-642-04081-8_1openalex-snapshot
Perspectives on Transactional Memory
inferred← citeshttps://doi.org/10.1007/978-3-642-15291-7_2openalex-snapshot
Transactional Mutex Locks
inferred← citeshttps://doi.org/10.1007/978-3-642-19448-1_14openalex-snapshot
Efficient Partial Roll-Backing Mechanism for Transactional Memory Systems
inferred← citeshttps://doi.org/10.1007/978-3-642-24568-8_13openalex-snapshot
Software Transactional Memory Validation – Time and Space Considerations
inferred← citeshttps://doi.org/10.1007/s00446-017-0305-3openalex-snapshot
Inherent limitations of hybrid transactional memory
inferred← citeshttps://doi.org/10.1007/s10766-008-0073-6openalex-snapshot
Nebelung: Execution Environment for Transactional OpenMP
inferred← citeshttps://doi.org/10.1007/s10766-010-0158-xopenalex-snapshot
Hybrid Transactional Memory with Pessimistic Concurrency Control
inferred← citeshttps://doi.org/10.1007/s11704-009-0028-0openalex-snapshot
Four styles of parallel and net programming
inferred← citeshttps://doi.org/10.1016/j.jpdc.2010.02.006openalex-snapshot
Adaptive locks: Combining transactions and locks for efficient concurrency
inferred← citeshttps://doi.org/10.1016/j.jpdc.2018.02.013openalex-snapshot
NVHT: An efficient key–value storage library for non-volatile memory
inferred← citeshttps://doi.org/10.1109/cgo.2013.6495000openalex-snapshot
On the platform specificity of STM instrumentation mechanisms
inferred← citeshttps://doi.org/10.1109/date.2012.6176429openalex-snapshot
TagTM - accelerating STMs with hardware tags for fast meta-data access
inferred← citeshttps://doi.org/10.1109/fpl.2010.64openalex-snapshot
Design and Implementation of Real-Time Transactional Memory
inferred← citeshttps://doi.org/10.1109/hpca.2008.4658646openalex-snapshot
Thread-safe dynamic binary translation using transactional memory
inferred← citeshttps://doi.org/10.1109/hpca.2018.00029openalex-snapshot
High-Performance GPU Transactional Memory via Eager Conflict Detection
inferred← citeshttps://doi.org/10.1109/icpp.2013.76openalex-snapshot
HEUSPEC: A Software Speculation Parallel Model
inferred← citeshttps://doi.org/10.1109/icsamos.2010.5642062openalex-snapshot
LV∗: A low complexity lazy versioning HTM infrastructure
inferred← citeshttps://doi.org/10.1109/iiswc.2008.4636089openalex-snapshot
STAMP: Stanford Transactional Applications for Multi-Processing
inferred← citeshttps://doi.org/10.1109/ipdps.2008.4536249openalex-snapshot
Intermediate checkpointing with conflicting access prediction in transactional memory systems
inferred← citeshttps://doi.org/10.1109/isca.2008.24openalex-snapshot
TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/ispa.2012.12openalex-snapshot
On Adaptive Contention Management Strategies for Software Transactional Memory
inferred← citeshttps://doi.org/10.1109/l-ca.2006.15openalex-snapshot
Disintermediated Active Communication
inferred← citeshttps://doi.org/10.1109/mascot.2009.5366659openalex-snapshot
TransPlant: A parameterized methodology for generating transactional memory workloads
inferred← citeshttps://doi.org/10.1109/micro.2010.23openalex-snapshot
A Dynamically Adaptable Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/mssc.2008.930935openalex-snapshot
The dawn of terascale computing
inferred← citeshttps://doi.org/10.1109/pact.2007.4336227openalex-snapshot
The OpenTM Transactional Application Programming Interface
inferred← citeshttps://doi.org/10.1109/pact.2007.74openalex-snapshot
The OpenTM Transactional Application Programming Interface
inferred← citeshttps://doi.org/10.1109/pact.2009.20openalex-snapshot
Adaptive Locks: Combining Transactions and Locks for Efficient Concurrency
inferred← citeshttps://doi.org/10.1109/pact.2017.28openalex-snapshot
A Generalized Framework for Automatic Scripting Language Parallelization
inferred← citeshttps://doi.org/10.1109/sc.2012.113openalex-snapshot
What scientific applications can benefit from hardware transactional memory?
inferred← citeshttps://doi.org/10.1109/tc.2011.230openalex-snapshot
LS-Sig: Locality-Sensitive Signatures for Transactional Memory
inferred← citeshttps://doi.org/10.1109/tpds.2012.138openalex-snapshot
Hardware Signature Designs to Deal with Asymmetry in Transactional Data Sets
inferred← citeshttps://doi.org/10.1145/1229428.1229484openalex-snapshot
Transactional programming in a multi-core environment
inferred← citeshttps://doi.org/10.1145/1248377.1248414openalex-snapshot
Nonblocking transactions without indirection using alert-on-update
inferred← citeshttps://doi.org/10.1145/1250662.1250667openalex-snapshot
Making the fast case common and the uncommon case simple in unbounded transactional memory
inferred← citeshttps://doi.org/10.1145/1250662.1250673openalex-snapshot
An effective hybrid transactional memory system with strong isolation guarantees
inferred← citeshttps://doi.org/10.1145/1250662.1250676openalex-snapshot
An integrated hardware-software approach to flexible transactional memory
inferred← citeshttps://doi.org/10.1145/1250734.1250744openalex-snapshot
Enforcing isolation and ordering in STM
inferred← citeshttps://doi.org/10.1145/1273440.1250667openalex-snapshot
Making the fast case common and the uncommon case simple in unbounded transactional memory
inferred← citeshttps://doi.org/10.1145/1273440.1250673openalex-snapshot
An effective hybrid transactional memory system with strong isolation guarantees
inferred← citeshttps://doi.org/10.1145/1273440.1250676openalex-snapshot
An integrated hardware-software approach to flexible transactional memory
inferred← citeshttps://doi.org/10.1145/1273442.1250744openalex-snapshot
Enforcing isolation and ordering in STM
inferred← citeshttps://doi.org/10.1145/1297027.1297042openalex-snapshot
Transactions with isolation and cooperation
inferred← citeshttps://doi.org/10.1145/1297105.1297042openalex-snapshot
Transactions with isolation and cooperation
inferred← citeshttps://doi.org/10.1145/1327171.1327181openalex-snapshot
Multithreaded software transactional memory and OpenMP
inferred← citeshttps://doi.org/10.1145/1345206.1345242openalex-snapshot
Software transactional memory for large scale clusters
inferred← citeshttps://doi.org/10.1145/1378533.1378564openalex-snapshot
Adaptive transaction scheduling for transactional memory systems
inferred← citeshttps://doi.org/10.1145/1400214.1400228openalex-snapshot
Software transactional memory
inferred← citeshttps://doi.org/10.1145/1449764.1449780openalex-snapshot
Design and implementation of transactional constructs for C/C++
inferred← citeshttps://doi.org/10.1145/1449955.1449780openalex-snapshot
Design and implementation of transactional constructs for C/C++
inferred← citeshttps://doi.org/10.1145/1454456.1454466openalex-snapshot
Software Transactional Memory: Why Is It Only a Research Toy?
inferred← citeshttps://doi.org/10.1145/1455770.1455800openalex-snapshot
Enforcing authorization policies using transactional memory introspection
inferred← citeshttps://doi.org/10.1145/1508244.1508262openalex-snapshot
Maximum benefit from a minimal HTM
inferred← citeshttps://doi.org/10.1145/1508244.1508263openalex-snapshot
Early experience with a commercial hardware transactional memory implementation
inferred← citeshttps://doi.org/10.1145/1508284.1508262openalex-snapshot
Maximum benefit from a minimal HTM
inferred← citeshttps://doi.org/10.1145/1508284.1508263openalex-snapshot
Early experience with a commercial hardware transactional memory implementation
inferred← citeshttps://doi.org/10.1145/1542452.1542465openalex-snapshot
Software transactional memory for multicore embedded systems
inferred← citeshttps://doi.org/10.1145/1542476.1542495openalex-snapshot
Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory
inferred← citeshttps://doi.org/10.1145/1543135.1542495openalex-snapshot
Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory
inferred← citeshttps://doi.org/10.1145/1543136.1542465openalex-snapshot
Software transactional memory for multicore embedded systems
inferred← citeshttps://doi.org/10.1145/1583991.1584049openalex-snapshot
Optimizing transactions for captured memory
inferred← citeshttps://doi.org/10.1145/1755913.1755918openalex-snapshot
Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack
inferred← citeshttps://doi.org/10.1145/1810085.1810097openalex-snapshot
Making nested parallel transactions practical using lightweight hardware support
inferred← citeshttps://doi.org/10.1145/1810479.1810530openalex-snapshot
Lightweight, robust adaptivity for software transactional memory
inferred← citeshttps://doi.org/10.1145/1950365.1950372openalex-snapshot
Hardware acceleration of transactional memory on commodity systems
inferred← citeshttps://doi.org/10.1145/1961295.1950372openalex-snapshot
Hardware acceleration of transactional memory on commodity systems
inferred← citeshttps://doi.org/10.1145/1961296.1950372openalex-snapshot
Hardware acceleration of transactional memory on commodity systems
inferred← citeshttps://doi.org/10.1145/1989493.1989501openalex-snapshot
Optimizing hybrid transactional memory
inferred← citeshttps://doi.org/10.1145/1995896.1995905openalex-snapshot
Multiset signatures for transactional memory
inferred← citeshttps://doi.org/10.1145/2155620.2155655openalex-snapshot
Hardware transactional memory for GPU architectures
inferred← citeshttps://doi.org/10.1145/2463676.2463720openalex-snapshot
Latch-free data structures for DBMS
inferred← citeshttps://doi.org/10.1145/2486159.2486165openalex-snapshot
Between all and nothing - versatile aborts in hardware transactional memory
inferred← citeshttps://doi.org/10.1145/2524211.2524216openalex-snapshot
Consistent, durable, and safe memory management for byte-addressable non volatile main memory
inferred← citeshttps://doi.org/10.1145/2528521.1508262openalex-snapshot
Maximum benefit from a minimal HTM
inferred← citeshttps://doi.org/10.1145/2528521.1508263openalex-snapshot
Early experience with a commercial hardware transactional memory implementation
inferred← citeshttps://doi.org/10.1145/2541228.2555306openalex-snapshot
Profile-guided transaction coalescing—lowering transactional overheads by merging transactions
inferred← citeshttps://doi.org/10.1145/3352460.3358270openalex-snapshot
FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory
inferred← citeshttps://doi.org/10.1145/3627535.3638504openalex-snapshot
Practical Hardware Transactional vEB Trees
inferred← citeshttps://doi.org/10.1155/2014/478013openalex-snapshot
Using Heuristic Value Prediction and Dynamic Task Granularity Resizing to Improve Software Speculation
inferred← citeshttps://doi.org/10.14288/1.0167110openalex-snapshot
GPU computing architecture for irregular parallelism
inferred← citeshttps://doi.org/10.17760/d20005070openalex-snapshot
Software transactional memory for multicore embedded systems
inferred← citeshttps://doi.org/10.2200/s00093ed1v01y200707cac003openalex-snapshot
Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency
inferred← citeshttps://doi.org/10.2200/s00272ed1v01y201006cac011openalex-snapshot
Transactional Memory, 2nd edition
inferred← citeshttps://doi.org/10.2200/s00499ed1v01y201304cac023openalex-snapshot
Shared-Memory Synchronization
inferred← citeshttps://doi.org/10.35662/unine-thesis-2210openalex-snapshot
Efficient Transactional Memory Runtimes for Unmanaged Environments
inferred← citeshttps://doi.org/10.35662/unine-thesis-2342openalex-snapshot
Software transactional memory building blocks
inferred← citeshttps://doi.org/10.4230/dagsemproc.07361.3openalex-snapshot
A Case for Deconstructing Hardware Transactional Memory Systems
inferred← citeshttps://doi.org/10.5445/ir/1000035636openalex-snapshot
Performance Optimization Strategies for Transactional Memory Applications
inferred← citeshttps://doi.org/10.5555/2492708.2492720openalex-snapshot
TagTM - accelerating STMs with hardware tags for fast meta-data access
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94452openalex-snapshot
Programming, debugging, profiling and optimizing transactional memory programs
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94562openalex-snapshot
Architectural support for high-performing hardware transactional memory systems
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94989openalex-snapshot
Towards lightweight and high-performance hardware transactional memory
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95388openalex-snapshot
Techniques for improving the performance of software transactional memory
inferred← citeshttps://doi.org/10.7275/6032276.0openalex-snapshot
Using Formal Methods to Verify Transactional Abstract Concurrency Control
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