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Optimal versus Heuristic Global Code Scheduling
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/9781118627372openalex-snapshot
Integer and Combinatorial Optimization
inferredcites →https://doi.org/10.1007/3-540-35767-x_15openalex-snapshot
Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors
inferredcites →https://doi.org/10.1007/3-540-45245-1_5openalex-snapshot
PROPAN: A Retargetable System for Postpass Optimisations and Analyses
inferredcites →https://doi.org/10.1109/cgo.2004.1281674openalex-snapshot
Exploring the performance potential of Itanium Processors with ILP-based scheduling
inferredcites →https://doi.org/10.1109/micro.1992.696999openalex-snapshot
Effective Compiler Support For Predicated Execution Using The Hyperblock
inferredcites →https://doi.org/10.1109/tc.1981.1675827openalex-snapshot
Trace Scheduling: A Technique for Global Microcode Compaction
inferredcites →https://doi.org/10.1145/113445.113466openalex-snapshot
Global instruction scheduling for superscalar machines
inferredcites →https://doi.org/10.1145/192724.192755openalex-snapshot
Characterizing the impact of predicated execution on branch prediction
inferredcites →https://doi.org/10.1145/267959.269966openalex-snapshot
Parallelizing nonnumerical code with selective scheduling and software pipelining
inferredcites →https://doi.org/10.1145/349299.349318openalex-snapshot
Optimal instruction scheduling using integer programming
inferredcites →https://doi.org/10.1145/384197.384217openalex-snapshot
ILP-based Instruction Scheduling for IA-64
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-20615-4_18openalex-snapshot
A Taxonomy of Methods and Models Used in Program Transformation and Parallelization
inferred← citeshttps://doi.org/10.1007/978-3-540-92990-1_18openalex-snapshot
Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors
inferred← citeshttps://doi.org/10.1007/978-3-642-13136-3_4openalex-snapshot
Dynamic Resource Tuning for Flexible Core Chip Multiprocessors
inferred← citeshttps://doi.org/10.1007/978-3-642-37051-9_2openalex-snapshot
Optimal and Heuristic Global Code Motion for Minimal Spilling
inferred← citeshttps://doi.org/10.1016/j.future.2011.10.004openalex-snapshot
Global register alias table: Boosting sequential program on multi-core
inferred← citeshttps://doi.org/10.1016/j.sysarc.2017.01.006openalex-snapshot
Increasing the efficiency and feasibility of configurable computing units
inferred← citeshttps://doi.org/10.1109/ipdpsw.2014.18openalex-snapshot
A New Dataflow Compiler IR for Accelerating Control-Intensive Code in Spatial Hardware
inferred← citeshttps://doi.org/10.1109/micro.2008.4771776openalex-snapshot
Strategies for mapping dataflow blocks to distributed hardware
inferred← citeshttps://doi.org/10.1109/micro.2010.30openalex-snapshot
Erasing Core Boundaries for Robust and Configurable Performance
inferred← citeshttps://doi.org/10.1109/micro.2012.36openalex-snapshot
MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP
inferred← citeshttps://doi.org/10.1109/micro.2012.37openalex-snapshot
Composite Cores: Pushing Heterogeneity Into a Core
inferred← citeshttps://doi.org/10.1145/1394608.1382140openalex-snapshot
Counting Dependence Predictors
inferred← citeshttps://doi.org/10.1145/1399972.1399981openalex-snapshot
Multitasking workload scheduling on flexible core chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1454115.1454142openalex-snapshot
Multitasking workload scheduling on flexible-core chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1498690.1498694openalex-snapshot
Optimal trace scheduling using enumeration
inferred← citeshttps://doi.org/10.1145/1508244.1508246openalex-snapshot
An evaluation of the TRIPS computer system
inferred← citeshttps://doi.org/10.1145/1629911.1630149openalex-snapshot
Efficient program scheduling for heterogeneous multi-core processors
inferred← citeshttps://doi.org/10.1145/1787275.1787330openalex-snapshot
Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses
inferred← citeshttps://doi.org/10.1145/1926367.1926373openalex-snapshot
Dynamic vectorization in the E2 dynamic multicore architecture
inferred← citeshttps://doi.org/10.1145/2000064.2000108openalex-snapshot
Dark silicon and the end of multicore scaling
inferred← citeshttps://doi.org/10.1145/2180887.2180896openalex-snapshot
Integrated Code Generation for Loops
inferred← citeshttps://doi.org/10.1145/2304576.2304580openalex-snapshot
Distributed replay protocol for distributed uniprocessors
inferred← citeshttps://doi.org/10.1145/2304576.2304592openalex-snapshot
Overcoming single-thread performance hurdles in the core fusion reconfigurable multicore architecture
inferred← citeshttps://doi.org/10.1145/2304576.2304600openalex-snapshot
CRQ-based fair scheduling on composable multicore architectures
inferred← citeshttps://doi.org/10.1145/2324876.2324879openalex-snapshot
Power Limitations and Dark Silicon Challenge the Future of Multicore
inferred← citeshttps://doi.org/10.1145/2390191.2390196openalex-snapshot
Improving performance per watt of asymmetric multi-core processors via online program phase classification and adaptive core morphing
inferred← citeshttps://doi.org/10.1145/2408776.2408797openalex-snapshot
Power challenges may end the multicore era
inferred← citeshttps://doi.org/10.1145/2509420.2512432openalex-snapshot
Preallocation instruction scheduling with register pressure minimization using a combinatorial optimization approach
inferred← citeshttps://doi.org/10.1145/2541940.2541954openalex-snapshot
The benefit of SMT in the multi-core era
inferred← citeshttps://doi.org/10.1145/2593069.2596674openalex-snapshot
Enabling Dynamic Heterogeneity Through Core-on-Core Stacking
inferred← citeshttps://doi.org/10.1145/2597809.2597815openalex-snapshot
Combinatorial spill code optimization and ultimate coalescing
inferred← citeshttps://doi.org/10.1145/2666357.2597815openalex-snapshot
Combinatorial spill code optimization and ultimate coalescing
inferred← citeshttps://doi.org/10.1145/2856125openalex-snapshot
A Survey of Techniques for Architecting and Managing Asymmetric Multicore Processors
inferred← citeshttps://doi.org/10.1145/2897937.2898009openalex-snapshot
Distributed scheduling for many-cores using cooperative game theory
inferred← citeshttps://doi.org/10.1145/2907950.2907951openalex-snapshot
A machine learning approach to mapping streaming workloads to dynamic multicore processors
inferred← citeshttps://doi.org/10.1145/2980930.2907951openalex-snapshot
A machine learning approach to mapping streaming workloads to dynamic multicore processors
inferred← citeshttps://doi.org/10.1145/3007787.3001183openalex-snapshot
Efficiently scaling out-of-order cores for simultaneous multithreading
inferred← citeshttps://doi.org/10.1145/3126523openalex-snapshot
A Study of Dynamic Phase Adaptation Using a Dynamic Multicore Processor
inferred← citeshttps://doi.org/10.5555/3201607.3201623openalex-snapshot
Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: a comprehensive parameter tuning
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