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Erasing Core Boundaries for Robust and Configurable Performance
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/dac.2002.1012681openalex-snapshot
Analysis of power consumption on switch fabrics in network routers
inferredcites →https://doi.org/10.1109/dsn.2004.1311888openalex-snapshot
The impact of technology scaling on lifetime reliability
inferredcites →https://doi.org/10.1109/dsn.2010.5544915openalex-snapshot
StageWeb: Interweaving pipeline stages into a wearout and variation tolerant CMP fabric
inferredcites →https://doi.org/10.1109/hpca.2008.4658644openalex-snapshot
Fundamental performance constraints in horizontal fusion of in-order cores
inferredcites →https://doi.org/10.1109/isca.2000.854380openalex-snapshot
Wattch: a framework for architectural-level power analysis and optimizations
inferredcites →https://doi.org/10.1109/isca.2004.1310781openalex-snapshot
The case for lifetime reliability-aware microprocessors
inferredcites →https://doi.org/10.1109/mc.2008.209openalex-snapshot
Amdahl's Law in the Multicore Era
inferredcites →https://doi.org/10.1109/mdt.2006.145openalex-snapshot
ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon
inferredcites →https://doi.org/10.1109/micro.1997.645806openalex-snapshot
The multicluster architecture: reducing cycle time through partitioning
inferredcites →https://doi.org/10.1109/micro.2000.898083openalex-snapshot
Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors
inferredcites →https://doi.org/10.1109/micro.2003.1253185openalex-snapshot
Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction
inferredcites →https://doi.org/10.1109/micro.2004.12openalex-snapshot
Conjoined-Core Chip Multiprocessing
inferredcites →https://doi.org/10.1109/micro.2007.10openalex-snapshot
Optimal versus Heuristic Global Code Scheduling
inferredcites →https://doi.org/10.1109/micro.2007.41openalex-snapshot
Composable Lightweight Processors
inferredcites →https://doi.org/10.1109/micro.2008.4771786openalex-snapshot
The StageNet fabric for constructing resilient multicore systems
inferredcites →https://doi.org/10.1109/mm.2005.110openalex-snapshot
Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation
inferredcites →https://doi.org/10.1109/mm.2005.35openalex-snapshot
Niagara: A 32-Way Multithreaded Sparc Processor
inferredcites →https://doi.org/10.1109/tdsc.2004.4openalex-snapshot
Commercial fault tolerance: a tale of two systems
inferredcites →https://doi.org/10.1109/tvlsi.2006.876103openalex-snapshot
HotSpot: a compact thermal modeling methodology for early-stage VLSI design
inferredcites →https://doi.org/10.1109/vlsic.2010.5560282openalex-snapshot
A 1.07 Tbit/s 128×128 swizzle network for SIMD processors
inferredcites →https://doi.org/10.1145/1028176.1006725openalex-snapshot
The Case for Lifetime Reliability-Aware Microprocessors
inferredcites →https://doi.org/10.1145/1151690.1151691openalex-snapshot
The Liberty Simulation Environment
inferredcites →https://doi.org/10.1145/1454115.1454124openalex-snapshot
Core cannibalization architecture
inferredcites →https://doi.org/10.1145/1555754.1555769openalex-snapshot
Architectural core salvaging in a multi-core processor for hard-error tolerance
inferredcites →https://doi.org/10.1145/360128.360165openalex-snapshot
Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors
inferredcites →https://doi.org/10.1145/513918.514051openalex-snapshot
Analysis of power consumption on switch fabrics in network routers
inferredcites →https://doi.org/10.5555/1331699.1331733openalex-snapshot
Composable Lightweight Processors
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-1-4471-6452-4_1openalex-snapshot
Towards a GPU Cloud: Benefits and Security Issues
inferred← citeshttps://doi.org/10.1109/euc.2014.10openalex-snapshot
Runtime Adaptation of Embedded Tasks with A-Priori Known Timing Behavior Utilizing On-Line Partner-Core Monitoring and Recovery
inferred← citeshttps://doi.org/10.1109/islped.2015.7273530openalex-snapshot
ReDEEM: A heterogeneous distributed microarchitecture for energy-efficient reliability
inferred← citeshttps://doi.org/10.1109/mcsoc.2013.36openalex-snapshot
Design and Implementation of an Efficient and Realistic Cooperative Core Architecture
inferred← citeshttps://doi.org/10.1109/micro.2012.36openalex-snapshot
MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00025openalex-snapshot
big.VLITTLE: On-Demand Data-Parallel Acceleration for Mobile Systems on Chip
inferred← citeshttps://doi.org/10.1145/2390191.2390196openalex-snapshot
Improving performance per watt of asymmetric multi-core processors via online program phase classification and adaptive core morphing
inferred← citeshttps://doi.org/10.1145/2491845.2491859openalex-snapshot
Rapid, low-power loop execution in a network of functional units
inferred← citeshttps://doi.org/10.1145/2801948.2801958openalex-snapshot
Performance and power simulation of a functional-unit-network processor with simplescalar and wattch
inferred← citeshttps://doi.org/10.1145/2856125openalex-snapshot
A Survey of Techniques for Architecting and Managing Asymmetric Multicore Processors
inferred← citeshttps://doi.org/10.1145/3466752.3480099openalex-snapshot
Software-Defined Vector Processing on Manycore Fabrics
inferred← citeshttps://doi.org/10.1145/3725843.3756070openalex-snapshot
SHADOW: Simultaneous Multi-Threading Architecture with Asymmetric Threads
inferred← citeshttps://doi.org/10.1504/ijhpsa.2013.058984openalex-snapshot
Amdahl's law in the era of process variation
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