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MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

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Power Aware Computing
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The OpenMP source code repository
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Performance estimation of multistreamed, superscalar processors
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Energy efficient CMOS microprocessor design
inferredcites →https://doi.org/10.1109/hpca.1999.744331openalex-snapshot
Out-of-order execution may not be cost-effective on processors featuring simultaneous multithreading
inferredcites →https://doi.org/10.1109/isca.1992.753311openalex-snapshot
An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads
inferredcites →https://doi.org/10.1109/isca.1995.524546openalex-snapshot
The SPLASH-2 programs: characterization and methodological considerations
inferredcites →https://doi.org/10.1109/isca.1995.524578openalex-snapshot
Simultaneous multithreading: Maximizing on-chip parallelism
inferredcites →https://doi.org/10.1109/isca.2008.22openalex-snapshot
Trading off Cache Capacity for Reliability to Enable Low Voltage Operation
inferredcites →https://doi.org/10.1109/isca.2008.23openalex-snapshot
Achieving Out-of-Order Performance with Almost In-Order Complexity
inferredcites →https://doi.org/10.1109/l-ca.2006.6openalex-snapshot
Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors
inferredcites →https://doi.org/10.1109/lpe.1994.573184openalex-snapshot
Low-power digital design
inferredcites →https://doi.org/10.1109/mc.2003.1250883openalex-snapshot
Dynamically tuning processor resources with adaptive processing
inferredcites →https://doi.org/10.1109/mc.2008.209openalex-snapshot
Amdahl's Law in the Multicore Era
inferredcites →https://doi.org/10.1109/micro.2007.10openalex-snapshot
Optimal versus Heuristic Global Code Scheduling
inferredcites →https://doi.org/10.1109/micro.2007.41openalex-snapshot
Composable Lightweight Processors
inferredcites →https://doi.org/10.1109/micro.2010.30openalex-snapshot
Erasing Core Boundaries for Robust and Configurable Performance
inferredcites →https://doi.org/10.1109/mm.2003.1196115openalex-snapshot
Hyperthreading technology in the netburst microarchitecture
inferredcites →https://doi.org/10.1109/tc.2004.46openalex-snapshot
Integrated analysis of power and performance for pipelined microprocessors
inferredcites →https://doi.org/10.1109/tc.2007.70771openalex-snapshot
Optimal Power/Performance Pipeline Depth for SMT in Scaled Technologies
inferredcites →https://doi.org/10.1145/1250662.1250686openalex-snapshot
Core fusion
inferredcites →https://doi.org/10.1145/1394608.1382169openalex-snapshot
Achieving Out-of-Order Performance with Almost In-Order Complexity
inferredcites →https://doi.org/10.1145/139669.139710openalex-snapshot
An elementary processor architecture with simultaneous instruction issuing from multiple threads
inferredcites →https://doi.org/10.1145/1508244.1508274openalex-snapshot
Accelerating critical section execution with asymmetric multi-core architectures
inferredcites →https://doi.org/10.1145/1669112.1669172openalex-snapshot
McPAT
inferredcites →https://doi.org/10.1145/1815961.1815965openalex-snapshot
WiDGET
inferredcites →https://doi.org/10.1145/1815961.1815966openalex-snapshot
Forwardflow
inferredcites →https://doi.org/10.1145/1854273.1854357openalex-snapshot
CoreGenesis
inferredcites →https://doi.org/10.1145/1880043.1880046openalex-snapshot
Federation
inferredcites →https://doi.org/10.1145/1926367.1926373openalex-snapshot
Dynamic vectorization in the E2 dynamic multicore architecture
inferredcites →https://doi.org/10.1145/2086696.2086698openalex-snapshot
ABS
inferredcites →https://doi.org/10.1145/2086696.2086701openalex-snapshot
Bahurupi
inferredcites →https://doi.org/10.1145/223982.223990openalex-snapshot
The SPLASH-2 programs
inferredcites →https://doi.org/10.1145/223982.224449openalex-snapshot
Simultaneous multithreading
inferredcites →https://doi.org/10.1145/360128.360136openalex-snapshot
On pipelining dynamic instruction scheduling logic
inferredcites →https://doi.org/10.5555/1331699.1331733openalex-snapshot
Composable Lightweight Processors

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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A Perspective on Dark Silicon
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Exploring ILP and TLP on a Polymorphic VLIW Processor
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A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode
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Design trade-offs for emerging HPC processors based on mobile market technology
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Exploiting Tightly-Coupled Cores
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Prevention from Soft Errors via Architecture Elasticity
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Dynamic power management techniques in multi-core architectures: A survey study
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Dynamic thread mapping for power-efficient many-core systems under performance constraints
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DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
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Enhancing Thread-Level Parallelism in Asymmetric Multicores using Transparent Instruction Offloading
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On dynamic polymorphing of a superscalar core for improving energy efficiency
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The heterogeneous block architecture
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Online mechanism for reliability and power-efficiency management of a dynamically reconfigurable core
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Energy Efficiency of Out-of-Order CPUs: Comparative Study and Microarchitectural Hotspot Characterization of RISC-V Designs
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Efficiently Scaling Out-of-Order Cores for Simultaneous Multithreading
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Accelerator Polymorphism: Transcending Domain-Specific Architectures with Robotics
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A Neural Network-Based Approach to Dynamic Core Morphing for AMPs
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A study of mobile device utilization
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Simultaneous and Speculative Thread Migration for Improving Energy Efficiency of Heterogeneous Core Architectures
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Dynamic Reconfiguration vs. DVFS: A Comparative Study on Power Efficiency of Processors
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Flicker
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The sharing architecture
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The benefit of SMT in the multi-core era
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RCS
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The sharing architecture
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The benefit of SMT in the multi-core era
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The sharing architecture
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The benefit of SMT in the multi-core era
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Datacenter Architectures for the Microservices Era
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