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Implementing Signatures for Transactional Memory
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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An Improved Construction for Counting Bloom Filters
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Network Applications of Bloom Filters: A Survey
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Efficient hardware hashing functions for high performance computers
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New efficient designs for XOR and XNOR functions on the transistor level
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Summary cache: a scalable wide-area Web cache sharing protocol
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Deep packet inspection using parallel Bloom filters
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Variability in architectural simulations of multi-threaded workloads
inferredcites →https://doi.org/10.1109/hpca.2006.1598134openalex-snapshot
LogTM: Log-based Transactional Memory
inferredcites →https://doi.org/10.1109/hpca.2007.346204openalex-snapshot
LogTM-SE: Decoupling Hardware Transactional Memory from Caches
inferredcites →https://doi.org/10.1109/isca.1993.698569openalex-snapshot
Transactional Memory: Architectural Support For Lock-free Data Structures
inferredcites →https://doi.org/10.1109/isca.1995.524546openalex-snapshot
The SPLASH-2 programs: characterization and methodological considerations
inferredcites →https://doi.org/10.1109/isca.2004.1310767openalex-snapshot
Transactional memory coherence and consistency
inferredcites →https://doi.org/10.1109/isca.2005.54openalex-snapshot
Virtualizing Transactional Memory
inferredcites →https://doi.org/10.1109/isca.2006.13openalex-snapshot
Bulk Disambiguation of Speculative Threads in Multiprocessors
inferredcites →https://doi.org/10.1109/lpe.2006.4271845openalex-snapshot
L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture
inferredcites →https://doi.org/10.1109/micro.2003.1253244openalex-snapshot
Scalable hardware memory disambiguation for high ILP processors
inferredcites →https://doi.org/10.1109/mm.2005.35openalex-snapshot
Niagara: A 32-Way Multithreaded Sparc Processor
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Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/1248377.1248428openalex-snapshot
Transactional memory and the birthday paradox
inferredcites →https://doi.org/10.1145/1250662.1250673openalex-snapshot
An effective hybrid transactional memory system with strong isolation guarantees
inferredcites →https://doi.org/10.1145/362686.362692openalex-snapshot
Space/time trade-offs in hash coding with allowable errors
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Practical performance of Bloom filters and parallel free-text searching
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Universal classes of hash functions (Extended Abstract)
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Exact and approximate membership testers
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An optimal Bloom filter replacement
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Hardware Approaches to Transactional Memory in Chip Multiprocessors
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A Program Logic for Dependence Analysis
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Approximate Data Dependence Profiling Based on Abstract Interval and Congruent Domains
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Conflict Detection in Hardware Transactional Memory
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The Processing-in-Memory Paradigm: Mechanisms to Enable Adoption
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SPMTM: A Novel ScratchPad Memory Based Hybrid Nested Transactional Memory Framework
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Application-Specific Signatures for Transactional Memory in Soft Processors
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Interval Filter: A Locality-Aware Alternative to Bloom Filters for Hardware Membership Queries by Interval Classification
inferred← citeshttps://doi.org/10.1007/978-3-642-23400-2_30openalex-snapshot
Unified Locality-Sensitive Signatures for Transactional Memory
inferred← citeshttps://doi.org/10.1007/s11227-016-1944-zopenalex-snapshot
Leveraging irrevocability to deal with signature saturation in hardware transactional memory
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A survey on optimizations towards best-effort hardware transactional memory
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An efficient deterministic record-replay with separate dependencies
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Lightweight Transactional Memory systems for NoCs based architectures: Design, implementation and comparison of two policies
inferred← citeshttps://doi.org/10.1016/j.jpdc.2010.03.006openalex-snapshot
Implementation tradeoffs in the design of flexible transactional memory support
inferred← citeshttps://doi.org/10.1016/j.jss.2016.03.045openalex-snapshot
Unveiling parallelization opportunities in sequential programs
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CCTR: An efficient point-to-point memory race recorder implemented in chunks
inferred← citeshttps://doi.org/10.1016/j.sysarc.2010.06.006openalex-snapshot
Hardware transactional memory: A high performance parallel programming model
inferred← citeshttps://doi.org/10.1049/el.2011.2798openalex-snapshot
Design of power-efficient parallel pipelined Bloom filter
inferred← citeshttps://doi.org/10.1049/iet-cdt.2014.0150openalex-snapshot
SkipCache: application aware cache management for chip multi‐processors
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SigNet: Network-on-chip filtering for coarse vector directories
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Leveraging HBM2 for Accelerating k-mer Counting with oneAPI on FPGAs
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iCFP: Tolerating all-level cache misses in in-order processors
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LiteTM: Reducing transactional state overhead
inferred← citeshttps://doi.org/10.1109/hpca.2011.5749718openalex-snapshot
Bloom Filter Guided Transaction Scheduling
inferred← citeshttps://doi.org/10.1109/hpca.2012.6169038openalex-snapshot
Architectural support for synchronization-free deterministic parallel programming
inferred← citeshttps://doi.org/10.1109/hpca.2012.6169039openalex-snapshot
Pacman: Tolerating asymmetric data races with unintrusive hardware
inferred← citeshttps://doi.org/10.1109/hpca.2013.6522346openalex-snapshot
In-network traffic regulation for Transactional Memory
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056033openalex-snapshot
Flask coherence: A morphable hybrid coherence protocol to balance energy, performance and scalability
inferred← citeshttps://doi.org/10.1109/hpca.2018.00029openalex-snapshot
High-Performance GPU Transactional Memory via Eager Conflict Detection
inferred← citeshttps://doi.org/10.1109/hpca.2018.00041openalex-snapshot
WIR: Warp Instruction Reuse to Minimize Repeated Computations in GPUs
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071113openalex-snapshot
Safety Hints for HTM Capacity Abort Mitigation
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Software Assisted Transact Cache to Support Efficient Unbounded Transactional Memory
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Hardware support for production run diagnosis of performance bugs
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Conflict detection via adaptive signature for software transactional memory
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Characterizing Loop-Level Communication Patterns in Shared Memory
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Efficient management of speculative data in hardware transactional memory systems
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Locality-aware adaptive grain signatures for Transactional Memories
inferred← citeshttps://doi.org/10.1109/ipdps.2011.81openalex-snapshot
Unified Signatures for Improving Performance in Transactional Memory
inferred← citeshttps://doi.org/10.1109/ipdps.2015.41openalex-snapshot
An Efficient Data-Dependence Profiler for Sequential and Parallel Programs
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Flexible Decoupled Transactional Memory Support
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TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory
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Rerun: Exploiting Episodes for Lightweight Memory Race Recording
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Atom-Aid: Detecting and Surviving Atomicity Violations
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HADES: Hardware-Assisted Distributed Transactions in the Age of Fast Networks and SmartNICs
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TLB Shootdown Mitigation for Low-Power Many-Core Servers with L1 Virtual Caches
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Fully pipelined bloom filter architecture
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The ZCache: Decoupling Ways and Associativity
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Efficient Memory Virtualization: Reducing Dimensionality of Nested Page Walks
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Lightweight Transactional Memory systems for large scale shared memory MPSoCs
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Improving Signatures by Locality Exploitation for Transactional Memory
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Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory
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A Segmented Bloom Filter Algorithm for Efficient Predictors
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Scalability Analysis of Signatures in Transactional Memory Systems
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Improving Signature Behavior by Irrevocability in Transactional Memory Systems
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LS-Sig: Locality-Sensitive Signatures for Transactional Memory
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Complexity-Effective Contention Management with Dynamic Backoff for Transactional Memory Systems
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A Case for Partitioned Bloom Filters
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Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory
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Hardware Signature Designs to Deal with Asymmetry in Transactional Data Sets
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Improving Utilization of Hardware Signatures in Transactional Memory
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Flexible Decoupled Transactional Memory Support
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A tagless coherence directory
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Architecting a chunk-based memory race recorder in modern CMPs
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Understanding bloom filter intersection for lazy address-set disambiguation
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Multiset signatures for transactional memory
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Optimizing throughput/power trade-offs in hardware transactional memory using DVFS and intelligent scheduling
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Application-specific signatures for transactional memory in soft processors
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Hardware transactional memory for GPU architectures
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Reuse-based online models for caches
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Consolidated conflict detection for hardware transactional memory
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Address Order Violation Detection with Parallel Counting Bloom Filters
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