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Efficient Memory Virtualization: Reducing Dimensionality of Nested Page Walks
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/12.926161openalex-snapshot
Uniprocessor virtual memory without TLBs
inferredcites →https://doi.org/10.1109/40.710872openalex-snapshot
Virtual memory in contemporary microprocessors
inferredcites →https://doi.org/10.1109/hpca.2001.903252openalex-snapshot
Reevaluating online superpage promotion with hardware support
inferredcites →https://doi.org/10.1109/hpca.2011.5749717openalex-snapshot
Shared last-level TLBs for chip multiprocessors
inferredcites →https://doi.org/10.1109/hpca.2014.6835964openalex-snapshot
Increasing TLB reach by exploiting clustering in page translations
inferredcites →https://doi.org/10.1109/icppw.2009.35openalex-snapshot
Characterizing the Performance of “Big Memory” on Blue Gene Linux
inferredcites →https://doi.org/10.1109/isca.1998.694775openalex-snapshot
Increasing TLB reach using superpages backed by shadow memory
inferredcites →https://doi.org/10.1109/isca.2002.1003578openalex-snapshot
Going the distance for TLB prefetching: an application-driven study
inferredcites →https://doi.org/10.1109/isca.2012.6237026openalex-snapshot
Reducing memory reference energy with opportunistic virtual caching
inferredcites →https://doi.org/10.1109/isca.2012.6237041openalex-snapshot
Revisiting hardware-assisted page walks for virtualized systems
inferredcites →https://doi.org/10.1109/mc.1974.6323581openalex-snapshot
Survey of virtual machine research
inferredcites →https://doi.org/10.1109/micro.2007.24openalex-snapshot
Implementing Signatures for Transactional Memory
inferredcites →https://doi.org/10.1109/micro.2012.32openalex-snapshot
CoLT: Coalesced Large-Reach TLBs
inferredcites →https://doi.org/10.1109/pact.2009.26openalex-snapshot
Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors
inferredcites →https://doi.org/10.1109/tc.2004.21openalex-snapshot
Concurrent support of multiple page sizes on a skewed associative TLB
inferredcites →https://doi.org/10.1145/1060289.1060307openalex-snapshot
Memory resource management in VMware ESX server
inferredcites →https://doi.org/10.1145/1165389.945462openalex-snapshot
Xen and the art of virtualization
inferredcites →https://doi.org/10.1145/1168857.1168860openalex-snapshot
A comparison of software and hardware techniques for x86 virtualization
inferredcites →https://doi.org/10.1145/1346281.1346286openalex-snapshot
Accelerating two-dimensional page walks for virtualized systems
inferredcites →https://doi.org/10.1145/139669.140406openalex-snapshot
Tradeoffs in supporting two page sizes
inferredcites →https://doi.org/10.1145/17356.17398openalex-snapshot
An in-cache address translation mechanism
inferredcites →https://doi.org/10.1145/1735970.1736060openalex-snapshot
Inter-core cooperative TLB for chip multiprocessors
inferredcites →https://doi.org/10.1145/1736020.1736060openalex-snapshot
Inter-core cooperative TLB for chip multiprocessors
inferredcites →https://doi.org/10.1145/1899928.1899930openalex-snapshot
The evolution of an x86 virtual machine monitor
inferredcites →https://doi.org/10.1145/1952682.1952710openalex-snapshot
Selective hardware/software memory virtualization
inferredcites →https://doi.org/10.1145/195470.195531openalex-snapshot
Surpassing the TLB performance of superpages with less operating system support
inferredcites →https://doi.org/10.1145/195473.195531openalex-snapshot
Surpassing the TLB performance of superpages with less operating system support
inferredcites →https://doi.org/10.1145/2150976.2150989openalex-snapshot
Cosmic rays don't strike twice
inferredcites →https://doi.org/10.1145/2366231.2337194openalex-snapshot
Reducing memory reference energy with opportunistic virtual caching
inferredcites →https://doi.org/10.1145/2366231.2337214openalex-snapshot
Revisiting hardware-assisted page walks for virtualized systems
inferredcites →https://doi.org/10.1145/2445572.2445574openalex-snapshot
TLB Improvements for Chip Multiprocessors
inferredcites →https://doi.org/10.1145/2485922.2485933openalex-snapshot
Improving virtualization in the presence of software managed translation lookaside buffers
inferredcites →https://doi.org/10.1145/2485922.2485943openalex-snapshot
Efficient virtual memory for big memory servers
inferredcites →https://doi.org/10.1145/2540708.2540741openalex-snapshot
Large-reach memory management unit caches
inferredcites →https://doi.org/10.1145/2678373.2665694openalex-snapshot
The Direct-to-Data (D2D) cache
inferredcites →https://doi.org/10.1145/279358.279388openalex-snapshot
Increasing TLB reach using superpages backed by shadow memory
inferredcites →https://doi.org/10.1145/545214.545237openalex-snapshot
Going the distance for TLB prefetching
inferredcites →https://doi.org/10.1145/800001.811668openalex-snapshot
Virtual memory, processes, and sharing in Multics
inferredcites →https://doi.org/10.1145/844128.844146openalex-snapshot
Memory resource management in VMware ESX server
inferredcites →https://doi.org/10.1145/945461.945462openalex-snapshot
Xen and the art of virtualization
inferredcites →https://doi.org/10.5555/1331699.1331713openalex-snapshot
Implementing Signatures for Transactional Memory
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/9781119785873.ch17openalex-snapshot
Unsupervised Learning in Accordance With New Aspects of Artificial Intelligence
inferred← citeshttps://doi.org/10.1007/978-3-030-60939-9_5openalex-snapshot
CoPTA: Contiguous Pattern Speculating TLB Architecture
inferred← citeshttps://doi.org/10.1007/978-3-031-01753-7openalex-snapshot
Hardware and Software Support for Virtualization
inferred← citeshttps://doi.org/10.1007/978-981-15-7981-3_46openalex-snapshot
Superpage-Friendly Page Table Design for Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1016/j.cosrev.2018.06.002openalex-snapshot
A survey of memory management techniques in virtualized systems
inferred← citeshttps://doi.org/10.1109/access.2020.2983065openalex-snapshot
TLB Coalescing for Multi-Grained Page Migration in Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/bigdata52589.2021.9672050openalex-snapshot
Efficient Huge Page Management with Xpage
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446100openalex-snapshot
Energy-efficient address translation
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00050openalex-snapshot
Dead Page and Dead Block Predictors: Cleaning TLBs and Caches Together
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00059openalex-snapshot
Improving GPU Multi-tenancy with Page Walk Stealing
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071061openalex-snapshot
Memory-Efficient Hashed Page Tables
inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00119openalex-snapshot
Gemina: A Coordinated and High-Performance Memory Deduplication Engine
inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00123openalex-snapshot
Marching Page Walks: Batching and Concurrent Page Table Walks for Enhancing GPU Throughput
inferred← citeshttps://doi.org/10.1109/iceic64972.2025.10879750openalex-snapshot
Expanding the PDE Cache by Exploiting Underutilized TLB Entries for Data-Intensive Workloads
inferred← citeshttps://doi.org/10.1109/ipdps49936.2021.00115openalex-snapshot
Performance Analysis of Scientific Computing Workloads on General Purpose TEEs
inferred← citeshttps://doi.org/10.1109/isai.2016.0015openalex-snapshot
Dynamic Page Size Adjustment in Operating System
inferred← citeshttps://doi.org/10.1109/isca.2016.67openalex-snapshot
Agile Paging: Exceeding the Best of Nested and Shadow Paging
inferred← citeshttps://doi.org/10.1109/isca.2018.00025openalex-snapshot
Scheduling Page Table Walks for Irregular GPU Applications
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00049openalex-snapshot
BabelFish: Fusing Address Translations for Containers
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00050openalex-snapshot
Enhancing and Exploiting Contiguity for Fast Memory Virtualization
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00089openalex-snapshot
The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework
inferred← citeshttps://doi.org/10.1109/ispass.2016.7482091openalex-snapshot
Observations and opportunities in architecting shared virtual memory for heterogeneous systems
inferred← citeshttps://doi.org/10.1109/micro.2018.00030openalex-snapshot
Scalable Distributed Last-Level TLBs Using Low-Latency Interconnects
inferred← citeshttps://doi.org/10.1109/micro.2018.00036openalex-snapshot
Neighborhood-Aware Address Translation for Irregular GPU Applications
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00023openalex-snapshot
CHiRP: Control-Flow History Reuse Prediction
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00046openalex-snapshot
Predicting Execution Times With Partial Simulations in Virtual Memory Research: Why and How
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00012openalex-snapshot
Elastic Translations: Fast Virtual Memory with Multiple Translation Sizes
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00031openalex-snapshot
STAR: Sub-Entry Sharing-Aware TLB for Multi-Instance GPU
inferred← citeshttps://doi.org/10.1109/pact58117.2023.00014openalex-snapshot
HugeGPT: Storing Guest Page Tables on Host Huge Pages to Accelerate Address Translation
inferred← citeshttps://doi.org/10.1109/qrs.2018.00015openalex-snapshot
BehaviorKI: Behavior Pattern Based Runtime Integrity Checking for Operating System Kernel
inferred← citeshttps://doi.org/10.1109/tc.2022.3145671openalex-snapshot
Accelerating Address Translation for Virtualization by Leveraging Hardware Mode
inferred← citeshttps://doi.org/10.1109/tc.2022.3191742openalex-snapshot
Towards High Performance and Efficient Memory Deduplication via Mixed Pages
inferred← citeshttps://doi.org/10.1145/2749469.2749471openalex-snapshot
Redundant memory mappings for fast access to large memories
inferred← citeshttps://doi.org/10.1145/2830772.2830773openalex-snapshot
Large pages and lightweight memory management in virtualized environments
inferred← citeshttps://doi.org/10.1145/2872887.2749471openalex-snapshot
Redundant memory mappings for fast access to large memories
inferred← citeshttps://doi.org/10.1145/2892242.2892258openalex-snapshot
Performance Implications of Extended Page Tables on Virtualized x86 Processors
inferred← citeshttps://doi.org/10.1145/2896377.2901456openalex-snapshot
Hash, Don't Cache (the Page Table)
inferred← citeshttps://doi.org/10.1145/2964791.2901456openalex-snapshot
Hash, Don't Cache (the Page Table)
inferred← citeshttps://doi.org/10.1145/2987550.2987551openalex-snapshot
A Case for Virtualizing Persistent Memory
inferred← citeshttps://doi.org/10.1145/3007611.2892258openalex-snapshot
Performance Implications of Extended Page Tables on Virtualized x86 Processors
inferred← citeshttps://doi.org/10.1145/3079856.3080209openalex-snapshot
Do-It-Yourself Virtual Memory Translation
inferred← citeshttps://doi.org/10.1145/3079856.3080210openalex-snapshot
Rethinking TLB Designs in Virtualized Environments
inferred← citeshttps://doi.org/10.1145/3079856.3080211openalex-snapshot
Hardware Translation Coherence for Virtualized Systems
inferred← citeshttps://doi.org/10.1145/3139645.3139652openalex-snapshot
Performance Implications of Extended Page Tables on Virtualized x86 Processors
inferred← citeshttps://doi.org/10.1145/3140659.3080209openalex-snapshot
Do-It-Yourself Virtual Memory Translation
inferred← citeshttps://doi.org/10.1145/3140659.3080210openalex-snapshot
Rethinking TLB Designs in Virtualized Environments
inferred← citeshttps://doi.org/10.1145/3140659.3080211openalex-snapshot
Hardware Translation Coherence for Virtualized Systems
inferred← citeshttps://doi.org/10.1145/3173162.3173203openalex-snapshot
Making Huge Pages Actually Useful
inferred← citeshttps://doi.org/10.1145/3273982.3273988openalex-snapshot
Hardware Translation Coherence for Virtualized Systems
inferred← citeshttps://doi.org/10.1145/3296957.3173203openalex-snapshot
Making Huge Pages Actually Useful
inferred← citeshttps://doi.org/10.1145/3297858.3304044openalex-snapshot
A Framework for Memory Oversubscription Management in Graphics Processing Units
inferred← citeshttps://doi.org/10.1145/3307650.3322224openalex-snapshot
Interplay between hardware prefetcher and page eviction policy in CPU-GPU unified virtual memory
inferred← citeshttps://doi.org/10.1145/3310133openalex-snapshot
Supporting Superpages and Lightweight Page Migration in Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1145/3343737.3343745openalex-snapshot
Thinking about A New Mechanism for Huge Page Management
inferred← citeshttps://doi.org/10.1145/3352460.3358294openalex-snapshot
Prefetched Address Translation
inferred← citeshttps://doi.org/10.1145/3373376.3378468openalex-snapshot
Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory Machines
inferred← citeshttps://doi.org/10.1145/3445814.3446709openalex-snapshot
Fast local page-tables for virtualized NUMA servers with vMitosis
inferred← citeshttps://doi.org/10.1145/3453933.3454012openalex-snapshot
Swift shadow paging (SSP): no write-protection but following TLB flushing
inferred← citeshttps://doi.org/10.1145/3453933.3454013openalex-snapshot
(No)Compromis: paging virtualization is not a fatality
inferred← citeshttps://doi.org/10.1145/3453933.3454018openalex-snapshot
Extending Intel PML for hardware-assisted working set size estimation of VMs
inferred← citeshttps://doi.org/10.1145/3459898.3463902openalex-snapshot
Compendia: reducing virtual-memory costs via selective densification
inferred← citeshttps://doi.org/10.1145/3466752.3480062openalex-snapshot
Trident: Harnessing Architectural Resources for All Page Sizes in x86 Processors
inferred← citeshttps://doi.org/10.1145/3503222.3507718openalex-snapshot
Every walk’s a hit: making page walks single-access cache hits
inferred← citeshttps://doi.org/10.1145/3547142openalex-snapshot
Reducing Minor Page Fault Overheads through Enhanced Page Walker
inferred← citeshttps://doi.org/10.1145/3576882.3617912openalex-snapshot
Lens: Experiencing Multi-level Page Tables at Close Quarters
inferred← citeshttps://doi.org/10.1145/3613424.3614276openalex-snapshot
Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources
inferred← citeshttps://doi.org/10.1145/3613424.3614293openalex-snapshot
Accelerating Extra Dimensional Page Walks for Confidential Computing
inferred← citeshttps://doi.org/10.1145/3613424.3623789openalex-snapshot
Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings
inferred← citeshttps://doi.org/10.1145/3620665.3640358openalex-snapshot
Direct Memory Translation for Virtualized Clouds
inferred← citeshttps://doi.org/10.1145/3620665.3640369openalex-snapshot
WASP: Workload-Aware Self-Replicating Page-Tables for NUMA Servers
inferred← citeshttps://doi.org/10.1145/3676641.3716027openalex-snapshot
Virtuoso: Enabling Fast and Accurate Virtual Memory Research via an Imitation-based Operating System Simulation Methodology
inferred← citeshttps://doi.org/10.1145/3725843.3756093openalex-snapshot
Learning to Walk: Architecting Learned Virtual Memory Translation
inferred← citeshttps://doi.org/10.1145/3735950.3735952openalex-snapshot
EMD: Fair and Efficient Dynamic Memory De-bloating of Transparent Huge Pages
inferred← citeshttps://doi.org/10.1145/3802921openalex-snapshot
Making Hardware Features Bespoke: Operating System Support for Bes-Mode Processes
inferred← citeshttps://doi.org/10.2172/1768054openalex-snapshot
Performance Analysis of Scientific Computing Workloads on Trusted Execution Environments
inferred← citeshttps://doi.org/10.2200/s00754ed1v01y201701cac038openalex-snapshot
Hardware and Software Support for Virtualization
inferred← citeshttps://doi.org/10.2200/s00795ed1v01y201708cac042openalex-snapshot
Architectural and Operating System Support for Virtual Memory
inferred← citeshttps://doi.org/10.26153/tsw/3003openalex-snapshot
Scalable virtual memory via tailored and larger page sizes
inferred← citeshttps://doi.org/10.3390/electronics10172058openalex-snapshot
Direct-Virtio: A New Direct Virtualized I/O Framework for NVMe SSDs
inferred← citeshttps://doi.org/10.48550/arxiv.1701.03499openalex-snapshot
VESPA: VIPT Enhancements for Superpage Accesses
inferred← citeshttps://doi.org/10.48550/arxiv.1804.11265openalex-snapshot
Mosaic: An Application-Transparent Hardware-Software Cooperative Memory Manager for GPUs
inferred← citeshttps://doi.org/10.48550/arxiv.2001.09991openalex-snapshot
Intel Page Modification Logging, a hardware virtualization feature: study and improvement for virtual machine working set estimation
inferred← citeshttps://doi.org/10.48550/arxiv.2002.01073openalex-snapshot
TLB and Pagewalk Performance in Multicore Architectures with Large Die-Stacked DRAM Cache
inferred← citeshttps://doi.org/10.48550/arxiv.2006.00380openalex-snapshot
Memory virtualization in virtualized systems: segmentation is better than paging
inferred← citeshttps://doi.org/10.48550/arxiv.2012.05079openalex-snapshot
Page Tables: Keeping them Flat and Hot (Cached)
inferred← citeshttps://doi.org/10.5075/epfl-thesis-6631openalex-snapshot
Multi-Gigabyte On-Chip DRAM Caches for Servers
inferred← citeshttps://doi.org/10.53375/ijecer.2023.341openalex-snapshot
Virtualization Maturity in Creating System VM: An Updated Performance Evaluation
inferred← citeshttps://doi.org/10.5555/3026877.3026931openalex-snapshot
Coordinated and efficient huge page management with ingens
inferred← citeshttps://doi.org/10.5821/dissertation-2117-403959openalex-snapshot
Advanced hardware prefetching in virtual memory systems
inferred← citeshttps://doi.org/10.5821/dissertation-2117-96333openalex-snapshot
Improving the performance and energy-efficiency of virtual memory
inferred← citeshttps://doi.org/10.70675/d3a42eadz5b5fz41bdzac06z4d1a9261f8ffopenalex-snapshot
Out of hypervisor (OoH) : when nested virtualization becomes practical
inferred← citeshttps://doi.org/10.7282/t3-m0cq-tt95openalex-snapshot
Improving and complementing virtual memory using hardware techniques
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