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ASR: Adaptive Selective Replication for CMP Caches
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-44587-0_1openalex-snapshot
SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance
inferredcites →https://doi.org/10.1023/b:supe.0000014800.27383.8fopenalex-snapshot
Dynamic Partitioning of Shared Cache Memory
inferredcites →https://doi.org/10.1109/4.400426openalex-snapshot
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
inferredcites →https://doi.org/10.1109/hpca.1997.569686openalex-snapshot
Reducing remote conflict misses: NUMA with remote cache versus COMA
inferredcites →https://doi.org/10.1109/hpca.2002.995703openalex-snapshot
A new memory monitoring scheme for memory-aware scheduling and partitioning
inferredcites →https://doi.org/10.1109/hpca.2004.10017openalex-snapshot
Organizing the Last Line of Defense before Hitting the Memory Wall for CMPs
inferredcites →https://doi.org/10.1109/hpca.2005.17openalex-snapshot
Improving Multiple-CMP Systems Using Token Coherence
inferredcites →https://doi.org/10.1109/hpca.2006.1598115openalex-snapshot
Last Level Cache (LLC) Performance of Data Mining Workloads On a CMP - A Case Study of Parallel Bioinformatics Workloads
inferredcites →https://doi.org/10.1109/isca.1989.714547openalex-snapshot
Inexpensive Implementations Of Set-Associativity
inferredcites →https://doi.org/10.1109/isca.1992.753306openalex-snapshot
Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures
inferredcites →https://doi.org/10.1109/isca.1995.524546openalex-snapshot
The SPLASH-2 programs: characterization and methodological considerations
inferredcites →https://doi.org/10.1109/isca.1998.694793openalex-snapshot
Flexible use of memory for replication/migration in cache-coherent DSM multiprocessors
inferredcites →https://doi.org/10.1109/isca.2005.39openalex-snapshot
Optimizing Replication, Communication, and Capacity Allocation in CMPs
inferredcites →https://doi.org/10.1109/isca.2005.8openalex-snapshot
Adaptive mechanisms and policies for managing cache hierarchies in chip multiprocessors
inferredcites →https://doi.org/10.1109/mc.2003.1178046openalex-snapshot
Simulating a $2M commercial server on a $2K PC
inferredcites →https://doi.org/10.1109/micro.2004.21openalex-snapshot
Managing Wire Delay in Large Chip-Multiprocessor Caches
inferredcites →https://doi.org/10.1109/mm.2003.1196114openalex-snapshot
Itanium 2 processor microarchitecture
inferredcites →https://doi.org/10.1109/mm.2005.34openalex-snapshot
Montecito: A Dual-Core, Dual-Thread Itanium Processor
inferredcites →https://doi.org/10.1145/1080695.1069999openalex-snapshot
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
inferredcites →https://doi.org/10.1145/1080695.1070001openalex-snapshot
Optimizing Replication, Communication, and Capacity Allocation in CMPs
inferredcites →https://doi.org/10.1145/1088149.1088154openalex-snapshot
A NUCA substrate for flexible CMP cache sharing
inferredcites →https://doi.org/10.1145/1150019.1136509openalex-snapshot
Cooperative Caching for Chip Multiprocessors
inferredcites →https://doi.org/10.1145/1168857.1168865openalex-snapshot
A regulated transitive reduction (RTR) for longer memory race recording
inferredcites →https://doi.org/10.1145/139669.139705openalex-snapshot
Comparative performance evaluation of cache-coherent NUMA and COMA architectures
inferredcites →https://doi.org/10.1145/195470.195485openalex-snapshot
Scheduling and page migration for multiprocessor compute servers
inferredcites →https://doi.org/10.1145/195473.195485openalex-snapshot
Scheduling and page migration for multiprocessor compute servers
inferredcites →https://doi.org/10.1145/237090.237205openalex-snapshot
Operating system support for improving data locality on CC-NUMA compute servers
inferredcites →https://doi.org/10.1145/566408.566444openalex-snapshot
Fine-grain CAM-tag cache resizing using miss tags
inferredcites →https://doi.org/10.1145/605397.605420openalex-snapshot
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
inferredcites →https://doi.org/10.1145/74925.74941openalex-snapshot
Inexpensive implementations of set-associativity
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Cooperative Caching for Chip Multiprocessors
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Multi-Core Cache Hierarchies
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ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors
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L1 Collective Cache: Managing Shared Data for Chip Multiprocessors
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A Novel Cache Organization for Tiled Chip Multiprocessor
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Last Bank: Dealing with Address Reuse in Non-Uniform Cache Architecture for CMPs
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Power-Efficient Spilling Techniques for Chip Multiprocessors
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Enhanced Adaptive Insertion Policy for Shared Caches
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Collaborative Memories in Clusters: Opportunities and Challenges
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Evaluation of the implementation cost of cache coherence protocols using omniscient actions
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Cluster Cache Monitor: Leveraging the Proximity Data in CMP
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An adaptive migration–replication scheme (AMR) for shared cache in chip multiprocessors
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Locality-aware data replication in the last-level cache for large scale multicores
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Exploring grouped coherence for clustered hierarchical cache
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FOS: a low-power cache organization for multicores
inferred← citeshttps://doi.org/10.1007/s11390-010-9321-5openalex-snapshot
Hierarchical Cache Directory for CMP
inferred← citeshttps://doi.org/10.1007/s11390-014-1459-0openalex-snapshot
DEAM: Decoupled, Expressive, Area-Efficient Metadata Cache
inferred← citeshttps://doi.org/10.1016/bs.adcom.2018.03.001openalex-snapshot
Dark Silicon and the History of Computing
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Exploring the relationship between architectures and management policies in the design of NUCA-based chip multicore systems
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An efficient cache flat storage organization for multithreaded workloads for low power processors
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A leakage-aware L2 cache management technique for producer–consumer sharing in low-power chip multiprocessors
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A hardware-efficient dual-source data replication and local broadcast mechanism in distributed shared caches
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Reliability improvement in private non-uniform cache architecture using two enhanced structures for coherence protocols and replacement policies
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An efficient adaptive block pinning for multicore architectures
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RACMan: Replication-aware cache management for manycore CMPs with private LLCs
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A perceptron-based replication scheme for managing the shared last level cache
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Partially shared cache and adaptive replacement algorithm for NoC-based many-core systems
inferred← citeshttps://doi.org/10.1109/access.2019.2959840openalex-snapshot
A Reuse-Degree Based Locality Classifier for Locality-Aware Data Replication
inferred← citeshttps://doi.org/10.1109/aspdac.2012.6165001openalex-snapshot
Proximity-Aware cache Replication
inferred← citeshttps://doi.org/10.1109/aspdac.2012.6165002openalex-snapshot
Dynamic reusability-based replication with network address mapping in CMPs
inferred← citeshttps://doi.org/10.1109/ccgrid.2013.16openalex-snapshot
Flexible Capacity Partitioning in Many-Core Tiled CMPs
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Designing and Modelling Selective Replication for Fault-Tolerant HPC Applications
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A Runtime Heuristic to Selectively Replicate Tasks for Application-Specific Reliability Targets
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PASCMP: A novel cache framework for data mining application
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Replication-aware Cache Management for CMPs with private LLCs
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An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload
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Re-NUCA: Boosting CMP Performance Through Block Replication
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Energy Behaviour of NUCA Caches in CMPs
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Avoiding common scalability pitfalls in shared-cache chip multiprocessor design
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Terascale chip multiprocessor memory hierarchy and programming model
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High performance cache block replication using re-reference probability in CMPs
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Optical overlay NUCA: A high speed substrate for shared L2 caches
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Adaptive Spill-Receive for robust high-performance caching in CMPs
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PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches
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Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches
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Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
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ESP-NUCA: A low-cost adaptive Non-Uniform Cache Architecture
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CloudCache: Expanding and shrinking private caches
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MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchy
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Adaptive Set-Granular Cooperative Caching
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Locality-aware data replication in the Last-Level Cache
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High performing cache hierarchies for server workloads: Relaxing inclusion to capture the latency benefits of exclusive caches
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Scaling distributed cache hierarchies through computation and data co-scheduling
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Analyzing and Leveraging Decoupled L1 Caches in GPUs
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A Novel Scheme to Balance the Cache Sharing in High Performance Computing System
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A sharing-aware actively pushing cache on CMP
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Ring data location prediction scheme for Non-Uniform Cache Architectures
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Bayesian theory oriented Optimal Data-Provider Selection for CMP
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Private cache partitioning: A method to reduce the off-chip missrate of concurrently executing applications in Chip-Multiprocessors
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An Improved Scheme of Victim Replication in Tiled Chip Multiprocessors
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SOC Estimation of Lead-Acid Batteries Based on UKF
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ARP: An adaptive replication policy in tiled Chip Multiprocessor
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A Partitioning Method of Cooperative Caching with Hit Frequency Counters for Many-Core Processors
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An Evaluation of Server Consolidation Workloads for Multi-Core Designs
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Understanding the applicability of CMP performance optimizations on data mining applications
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DiCo-CMP: Efficient cache coherency in tiled CMP architectures
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Efficient shared cache management through sharing-aware replacement and streaming-aware insertion policy
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Intra-application cache partitioning
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Exploiting set-level non-uniformity of capacity demand to enhance CMP cooperative caching
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DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors
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T-NUCA - a novel approach to non-uniform access latency cache architectures for 3D CMPs
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RRR: Robust runtime reconfigurable shared cache management scheme for GPGPUs
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Cache Management with Partitioning-Aware Eviction and Thread-Aware Insertion/Promotion Policy
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Modeling and Single-Pass Simulation of CMP Cache Capacity and Accessibility
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Nahalal: Cache Organization for Chip Multiprocessors
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Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow
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Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
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Synergistic TLBs for High Performance Address Translation in Chip Multiprocessors
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Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors
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Cache-Conscious Wavefront Scheduling
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Farewell My Shared LLC! A Case for Private Die-Stacked DRAM Caches for Servers
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Jumanji: The Case for Dynamic NUCA in the Datacenter
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Selective Replication in Memory-Side GPU Caches
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Stream-Based Data Placement for Near-Data Processing with Extended Memory
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Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures
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Fast Hierarchical Cache Directory: A Scalable Cache Organization for Large-Scale CMP
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The Power of Priority: NoC Based Distributed Cache Coherency
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SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors
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DDCache: Decoupled and Delegable Cache Data and Metadata
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POPS: Coherence Protocol Optimization for Both Private and Shared Data
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Scalable Proximity-Aware Cache Replication in Chip Multiprocessors
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Meeting midway: improving CMP performance with memory-side prefetching
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OSPREY: Implementation of Memory Consistency Models for Cache Coherence Protocols involving Invalidation-Free Data Access
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Nexus: A New Approach to Replication in Distributed Shared Caches
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Dynamic Thread Partition Algorithm Based on Sharing Data on CMP
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An Exploration of Page Replication for NoC-Based On-Chip Distributed Memory Systems
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Analysis of Performance Dependencies in NUCA-Based CMP Systems
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A novel migration-based NUCA design for Chip Multiprocessors
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Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support
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TD-NUCA: Runtime Driven Management of NUCA Caches in Task Dataflow Programming Models
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ICCI: In-Cache Coherence Information
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An Efficient Hybrid-Switched Network-on-Chip for Chip Multiprocessors
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Thread Criticality Assisted Replication and Migration for Chip Multiprocessor Caches
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Modeling and Stack Simulation of CMP Cache Capacity and Accessibility
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A Direct Coherence Protocol for Many-Core Chip Multiprocessors
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Distributed Cooperative Caching: An Energy Efficient Memory Scheme for Chip Multiprocessors
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Codesign of NoC and Cache Organization for Reducing Access Latency in Chip Multiprocessors
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Hierarchical Hybrid Memory Management in OS for Tiered Memory Systems
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Exploiting Replicated Cache Blocks to Reduce L2 Cache Leakage in CMPs
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Fine-grained adaptive CMP cache sharing through access history exploitation
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Cooperative Caching for Chip Multiprocessors
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CMP cache performance projection
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Virtual hierarchies to support server consolidation
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Interconnect design considerations for large NUCA caches
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Virtual hierarchies to support server consolidation
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Interconnect design considerations for large NUCA caches
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Cooperative cache partitioning for chip multiprocessors
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Utilizing shared data in chip multiprocessors with the Nahalal architecture
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Distributed cooperative caching
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Improving support for locality and fine-grain sharing in chip multiprocessors
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Leveraging on-chip networks for data cache migration in chip multiprocessors
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Dynamic cache clustering for chip multiprocessors
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An analysis of on-chip interconnection networks for large-scale chip multiprocessors
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Cache topology aware computation mapping for multicores
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Cache topology aware computation mapping for multicores
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Replication-aware leakage management in chip multiprocessors with private L2 cache
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NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
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Evaluating placement policies for managing capacity sharing in CMP architectures with private caches
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Locality & utility co-optimization for practical capacity management of shared last level caches
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A collaborative memory system for high-performance and cost-effective clustered architectures
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A survey on cache tuning from a power/energy perspective
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Location-aware cache management for many-core processors with deep cache hierarchy
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Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs
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Exploiting replication to improve performances of NUCA-based CMP systems
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Author retrospective for a NUCA substrate for flexible CMP cache sharing
inferred← citeshttps://doi.org/10.1145/2632217openalex-snapshot
Revisiting LP-NUCA Energy Consumption
inferred← citeshttps://doi.org/10.1145/2644865.2541976openalex-snapshot
Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs
inferred← citeshttps://doi.org/10.1145/2654822.2541976openalex-snapshot
Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs
inferred← citeshttps://doi.org/10.1145/2807591.2807649openalex-snapshot
Automatic sharing classification and timely push for cache-coherent systems
inferred← citeshttps://doi.org/10.1145/2925426.2926258openalex-snapshot
Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration
inferred← citeshttps://doi.org/10.1145/3307650.3322235openalex-snapshot
Adaptive memory-side last-level GPU caching
inferred← citeshttps://doi.org/10.1145/3410463.3414623openalex-snapshot
Analyzing and Leveraging Shared L1 Caches in GPUs
inferred← citeshttps://doi.org/10.1145/3613424.3623778openalex-snapshot
Affinity Alloc: Taming Not-So Near-Data Computing
inferred← citeshttps://doi.org/10.1145/3650200.3656604openalex-snapshot
NUCAlloc: Fine-Grained Block Placement in Hashed Last-Level NUCA Caches
inferred← citeshttps://doi.org/10.1145/3695053.3731061openalex-snapshot
NUPEA: Optimizing Critical Loads on Spatial Dataflow Architectures via Non-Uniform Processing-Element Access
inferred← citeshttps://doi.org/10.11606/d.3.2011.tde-31082011-163312openalex-snapshot
Power Laws na modelagem de caches de microprocessadores.
inferred← citeshttps://doi.org/10.14288/1.0166749openalex-snapshot
Locality and scheduling in the massively multithreaded era
inferred← citeshttps://doi.org/10.15308/sinteza-2023-159-165openalex-snapshot
Scratchpad Memory Unit in Hybrid Control-flow and Dataflow Architectures
inferred← citeshttps://doi.org/10.15623/ijret.2013.0214009openalex-snapshot
CMP CACHE ARCHITECTURES - A SURVEY
inferred← citeshttps://doi.org/10.1587/transfun.e96.a.1293openalex-snapshot
Bayesian Theory Based Adaptive Proximity Data Accessing for CMP Caches
inferred← citeshttps://doi.org/10.1587/transinf.2022edl8002openalex-snapshot
A Two-Level Cache Aware Adaptive Data Replication Mechanism for Shared LLC
inferred← citeshttps://doi.org/10.21220/s2-a01c-6214openalex-snapshot
Rethinking Cache Hierarchy And Interconnect Design For Next-Generation Gpus
inferred← citeshttps://doi.org/10.2200/s00365ed1v01y201105cac017openalex-snapshot
Multi-Core Cache Hierarchies
inferred← citeshttps://doi.org/10.2200/s00644ed1v01y201505cac031openalex-snapshot
Die-stacking Architecture
inferred← citeshttps://doi.org/10.26053/0h-65gq-7400openalex-snapshot
Managing data locality in future memory hierarchies using a hardware software codesign approach
inferred← citeshttps://doi.org/10.48550/arxiv.1603.09274openalex-snapshot
A Survey on Hardware and Software Support for Thread Level Parallelism
inferred← citeshttps://doi.org/10.4995/thesis/10251/165254openalex-snapshot
Novel Cache Hierarchies with Photonic Interconnects for Chip Multiprocessors
inferred← citeshttps://doi.org/10.5120/1131-1482openalex-snapshot
Adaptive Zone-Aware Multi-bank on Chip last level L2 Cache Partitioning for Chip Multiprocessors
inferred← citeshttps://doi.org/10.5121/ijcseit.2013.3201openalex-snapshot
Phase-Priority Based Directory Coherence for Multicore Processor
inferred← citeshttps://doi.org/10.5555/1413370.1413399openalex-snapshot
A novel migration-based NUCA design for chip multiprocessors
inferred← citeshttps://doi.org/10.5555/2523721.2523752openalex-snapshot
Jigsaw: scalable software-defined caches
inferred← citeshttps://doi.org/10.5555/2872599.2872608openalex-snapshot
Sharer status-based caching in tiled multiprocessor systems-on-chip
inferred← citeshttps://doi.org/10.5772/9454openalex-snapshot
Cache Coherence Protocols for Many-Core CMPs
inferred← citeshttps://doi.org/10.5821/dissertation-2117-336238openalex-snapshot
Runtime-assisted coherent caching
inferred← citeshttps://doi.org/10.5821/dissertation-2117-93335openalex-snapshot
Improving cache Behavior in CMP architectures throug cache partitioning techniques
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94560openalex-snapshot
Managing dynamic non-uiform cache architectures
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94566openalex-snapshot
Adaptive memory hierarchies for next generation tiled microarchitectures
inferred← citeshttps://doi.org/10.5821/dissertation-2117-96603openalex-snapshot
Reliability for exascale computing : system modelling and error mitigation for task-parallel HPC applications
inferred← citeshttps://doi.org/10.7916/d8-a78j-z392openalex-snapshot
Scalable Emulation of Heterogeneous Systems
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