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Adaptive Flow Control for Robust Performance and Energy
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-540-85451-7_97openalex-snapshot
Reducing Packet Dropping in a Bufferless NoC
inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot
Simics: A full system simulation platform
inferredcites →https://doi.org/10.1109/90.469955openalex-snapshot
A performance model of deflection routing in multibuffer networks with nonuniform traffic
inferredcites →https://doi.org/10.1109/date.2004.1269001openalex-snapshot
Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip
inferredcites →https://doi.org/10.1109/hpca.2001.903268openalex-snapshot
A delay model and speculative architecture for pipelined routers
inferredcites →https://doi.org/10.1109/infcom.1989.101529openalex-snapshot
Comparison of deflection and store-and-forward techniques in the Manhattan Street and Shuffle-Exchange Networks
inferredcites →https://doi.org/10.1109/isca.1995.524546openalex-snapshot
The SPLASH-2 programs: characterization and methodological considerations
inferredcites →https://doi.org/10.1109/isca.2004.1310774openalex-snapshot
Low-latency virtual-channel routers for on-chip networks
inferredcites →https://doi.org/10.1109/ispass.2009.4919636openalex-snapshot
GARNET: A detailed on-chip network model inside a full-system simulator
inferredcites →https://doi.org/10.1109/isscc.2007.373606openalex-snapshot
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS
inferredcites →https://doi.org/10.1109/micro.2002.1176258openalex-snapshot
Orion: a power-performance simulator for interconnection networks
inferredcites →https://doi.org/10.1109/mm.2003.1196116openalex-snapshot
The AMD opteron processor for multiprocessor servers
inferredcites →https://doi.org/10.1109/mm.2005.35openalex-snapshot
Niagara: A 32-Way Multithreaded Sparc Processor
inferredcites →https://doi.org/10.1109/nocs.2010.10openalex-snapshot
Evaluating Bufferless Flow Control for On-chip Networks
inferredcites →https://doi.org/10.1109/tcom.1964.1088883openalex-snapshot
On Distributed Communications Networks
inferredcites →https://doi.org/10.1109/vlsic.2008.4585952openalex-snapshot
Next generation Intel® micro-architecture (Nehalem) clocking architecture
inferredcites →https://doi.org/10.1117/12.932535openalex-snapshot
Architecture And Applications Of The HEP Multiprocessor Computer System
inferredcites →https://doi.org/10.1145/1028176.1006717openalex-snapshot
Low-Latency Virtual-Channel Routers for On-Chip Networks
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/1127908.1127977openalex-snapshot
Evaluation of on-chip networks using deflection routing
inferredcites →https://doi.org/10.1145/1555754.1555781openalex-snapshot
A case for bufferless routing in on-chip networks
inferredcites →https://doi.org/10.1145/871506.871531openalex-snapshot
Leakage power modeling and optimization in interconnection networks
inferredcites →https://doi.org/10.1145/97444.97452openalex-snapshot
The chaos router: a practical application of randomization in network routing
inferredcites →https://doi.org/10.5555/774861.774893openalex-snapshot
Orion: a power-performance simulator for interconnection networks
inferredcites →https://doi.org/10.5555/956417.956568openalex-snapshot
Power-driven design of router microarchitectures in on-chip networks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Bufferless and Minimally-Buffered Deflection Routing
inferred← citeshttps://doi.org/10.1007/978-3-319-27119-4_14openalex-snapshot
HVCRouter: Energy Efficient Network-on-Chip Router with Heterogeneous Virtual Channels
inferred← citeshttps://doi.org/10.1007/978-3-319-30695-7_3openalex-snapshot
CASCADE: Congestion Aware Switchable Cycle Adaptive Deflection Router
inferred← citeshttps://doi.org/10.1007/s11227-015-1407-yopenalex-snapshot
Dual-mode inter-router communication channel for deflection-routed networks-on-chip
inferred← citeshttps://doi.org/10.1007/s11390-015-1505-6openalex-snapshot
Exploring Heterogeneous NoC Design Space in Heterogeneous GPU-CPU Architectures
inferred← citeshttps://doi.org/10.1016/bs.adcom.2021.12.002openalex-snapshot
The design of an energy-efficient deflection-based on-chip network
inferred← citeshttps://doi.org/10.1016/j.compeleceng.2014.07.012openalex-snapshot
A survey on energy-efficient methodologies and architectures of network-on-chip
inferred← citeshttps://doi.org/10.1016/j.jksuci.2015.11.002openalex-snapshot
The efficiency of buffer and buffer-less data-flow control schemes for congestion avoidance in Networks on Chip
inferred← citeshttps://doi.org/10.1016/j.micpro.2014.07.007openalex-snapshot
LDBR: Low-deflection bufferless router for cost-sensitive network-on-chip design
inferred← citeshttps://doi.org/10.1016/j.micpro.2017.07.004openalex-snapshot
Problems and challenges of emerging technology networks−on−chip: A review
inferred← citeshttps://doi.org/10.1016/j.sysarc.2020.101832openalex-snapshot
Efficient bypass in mesh and torus NoCs
inferred← citeshttps://doi.org/10.1109/csci.2016.0117openalex-snapshot
A Perspective from Exploiting Heterogeneity on Networks-on-Chip Based on Dark Silicon Mitigation
inferred← citeshttps://doi.org/10.1109/hpca.2011.5749724openalex-snapshot
CHIPPER: A low-complexity bufferless deflection router
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835940openalex-snapshot
MP3: Minimizing performance penalty for power-gating of Clos network-on-chip
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00063openalex-snapshot
Pitstop: Enabling a Virtual Network Free Network-on-Chip
inferred← citeshttps://doi.org/10.1109/iccd.2013.6657068openalex-snapshot
SLIDER: Smart Late Injection DEflection Router for mesh NoCs
inferred← citeshttps://doi.org/10.1109/ipdpsw.2012.119openalex-snapshot
Energy-Efficient and Fault-Tolerant Unified Buffer and Bufferless Crossbar Architecture for NoCs
inferred← citeshttps://doi.org/10.1109/isca.2018.00064openalex-snapshot
Synchronized Progress in Interconnection Networks (SPIN): A New Theory for Deadlock Freedom
inferred← citeshttps://doi.org/10.1109/iwqos.2014.6914305openalex-snapshot
QBLESS: A case for QoS-aware bufferless NoCs
inferred← citeshttps://doi.org/10.1109/mcsoc.2012.25openalex-snapshot
Throttling Control for Bufferless Routing in On-chip Networks
inferred← citeshttps://doi.org/10.1109/micro.2012.33openalex-snapshot
NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers
inferred← citeshttps://doi.org/10.1109/nocarc.2018.8541147openalex-snapshot
Efficient Router Bypass via Hybrid Flow Control
inferred← citeshttps://doi.org/10.1109/nocs.2012.8openalex-snapshot
MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect
inferred← citeshttps://doi.org/10.1109/tcad.2020.3012170openalex-snapshot
Aggressive Fine-Grained Power Gating of NoC Buffers
inferred← citeshttps://doi.org/10.1109/tcad.2020.3037310openalex-snapshot
A Deflection-Based Deadlock Recovery Framework to Achieve High Throughput for Faulty NoCs
inferred← citeshttps://doi.org/10.1109/vlsid.2015.86openalex-snapshot
Smart Port Allocation for Adaptive NoC Routers
inferred← citeshttps://doi.org/10.1109/vlsid.2018.93openalex-snapshot
An Adaptive Deflection Router with Dual Injection and Ejection Units for Mesh NoCs
inferred← citeshttps://doi.org/10.1145/2342356.2342436openalex-snapshot
On-chip networks from a networking perspective
inferred← citeshttps://doi.org/10.1145/2377677.2377757openalex-snapshot
On-chip networks from a networking perspective
inferred← citeshttps://doi.org/10.1145/3658617.3697555openalex-snapshot
A Buffer Reservation Scheduling Strategy for Enhancing Performance of NoC Router Bypassing
inferred← citeshttps://doi.org/10.1155/2014/691865openalex-snapshot
Ephedrine QoS: An Antidote to Slow, Congested, Bufferless NoCs
inferred← citeshttps://doi.org/10.1184/r1/6468458openalex-snapshot
Bufferless and Minimally-Buffered Deflection Routing
inferred← citeshttps://doi.org/10.1184/r1/6468887openalex-snapshot
HiRD: A Low-Complexity, Energy-Efficient Hierarchical Ring Interconnect
inferred← citeshttps://doi.org/10.1184/r1/6468944openalex-snapshot
Investigating the Viability of Bufferless NoCs in Modern Chip Multi-processor Systems
inferred← citeshttps://doi.org/10.1184/r1/6469019openalex-snapshot
MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect
inferred← citeshttps://doi.org/10.2200/s00772ed1v01y201704cac040openalex-snapshot
On-Chip Networks, Second Edition
inferred← citeshttps://doi.org/10.5555/2485288.2485665openalex-snapshot
DeBAR: deflection based adaptive router with minimal buffering
inferred← citeshttps://doi.org/10.5573/ieek.2013.50.11.108openalex-snapshot
A Deflection Routing using Location Based Priority in Network-on-Chip
inferred← citeshttps://doi.org/10.70675/6ee3d5c1zfa27z4edbz8ff2z9ac3b7eebfaaopenalex-snapshot
Exploration of multicore systems based on silicon integrated communication networks
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