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Memory Architecture for Integrating Emerging Memory Technologies
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/hpca.1995.386537openalex-snapshot
Access ordering and memory-conscious cache utilization
inferredcites →https://doi.org/10.1109/hpca.1999.744334openalex-snapshot
Impulse: building a smarter memory controller
inferredcites →https://doi.org/10.1109/hpca.2001.903272openalex-snapshot
Reducing DRAM latencies with an integrated memory hierarchy design
inferredcites →https://doi.org/10.1109/hpca.2005.2openalex-snapshot
A Performance Comparison of DRAM Memory System Optimizations for SMT Processors
inferredcites →https://doi.org/10.1109/hpca.2007.346190openalex-snapshot
Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling
inferredcites →https://doi.org/10.1109/hpca.2007.346206openalex-snapshot
A Burst Scheduling Access Reordering Mechanism
inferredcites →https://doi.org/10.1109/hpca.2009.4798259openalex-snapshot
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
inferredcites →https://doi.org/10.1109/hpca.2010.5416645openalex-snapshot
Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing
inferredcites →https://doi.org/10.1109/hpca.2010.5416650openalex-snapshot
A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement
inferredcites →https://doi.org/10.1109/hpca.2010.5416658openalex-snapshot
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers
inferredcites →https://doi.org/10.1109/isca.2008.21openalex-snapshot
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach
inferredcites →https://doi.org/10.1109/isca.2008.7openalex-snapshot
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
inferredcites →https://doi.org/10.1109/jssc.2003.822773openalex-snapshot
A Fully Integrated On-Chip DC–DC Conversion and Power Management System
inferredcites →https://doi.org/10.1109/micro.2004.4openalex-snapshot
Adaptive History-Based Memory Schedulers
inferredcites →https://doi.org/10.1109/micro.2008.4771791openalex-snapshot
Prefetch-Aware DRAM Controllers
inferredcites →https://doi.org/10.1109/micro.2008.4771792openalex-snapshot
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency
inferredcites →https://doi.org/10.1109/mm.2006.1openalex-snapshot
Adaptive History-Based Memory Schedulers for Modern Processors
inferredcites →https://doi.org/10.1109/mm.2006.82openalex-snapshot
The M5 Simulator: Modeling Networked Systems
inferredcites →https://doi.org/10.1109/pesc.2004.1354830openalex-snapshot
A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control
inferredcites →https://doi.org/10.1145/1394608.1382128openalex-snapshot
Parallelism-Aware Batch Scheduling
inferredcites →https://doi.org/10.1145/1394608.1382172openalex-snapshot
Self-Optimizing Memory Controllers
inferredcites →https://doi.org/10.1145/1555754.1555758openalex-snapshot
Architecting phase change memory as a scalable dram alternative
inferredcites →https://doi.org/10.1145/1555754.1555759openalex-snapshot
A durable and energy efficient main memory using phase change memory technology
inferredcites →https://doi.org/10.1145/1555754.1555760openalex-snapshot
Scalable high performance main memory system using phase-change memory technology
inferredcites →https://doi.org/10.1145/1555754.1555761openalex-snapshot
Hybrid cache architecture with disparate memory technologies
inferredcites →https://doi.org/10.1145/1555754.1555789openalex-snapshot
Disaggregated memory for expansion and sharing in blade servers
inferredcites →https://doi.org/10.1145/1654059.1654102openalex-snapshot
Future scaling of processor-memory interfaces
inferredcites →https://doi.org/10.1145/1669112.1669117openalex-snapshot
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
inferredcites →https://doi.org/10.1145/1815961.1815978openalex-snapshot
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
inferredcites →https://doi.org/10.1145/1815961.1815983openalex-snapshot
Rethinking DRAM design and organization for energy-constrained multi-cores
inferredcites →https://doi.org/10.1145/1854273.1854314openalex-snapshot
Handling the problems and opportunities posed by multiple on-chip memory controllers
inferredcites →https://doi.org/10.1145/232973.232983openalex-snapshot
Memory bandwidth limitations of future microprocessors
inferredcites →https://doi.org/10.1145/360128.360134openalex-snapshot
A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality
inferredcites →https://doi.org/10.1145/379240.379252openalex-snapshot
Concurrency, latency, or system overhead
inferredcites →https://doi.org/10.1145/511334.511343openalex-snapshot
Symbiotic jobscheduling with priorities for a simultaneous multithreading processor
inferredcites →https://doi.org/10.1145/511399.511343openalex-snapshot
Symbiotic jobscheduling with priorities for a simultaneous multithreading processor
inferredcites →https://doi.org/10.1145/605397.605403openalex-snapshot
Automatically characterizing large scale program behavior
inferredcites →https://doi.org/10.1145/635508.605403openalex-snapshot
Automatically characterizing large scale program behavior
inferredcites →https://doi.org/10.1147/rd.524.0465openalex-snapshot
Phase-change random access memory: A scalable technology
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/9781118760475.ch06openalex-snapshot
3D Stacking of RAM–Processor Chips Using TSV
inferred← citeshttps://doi.org/10.1007/s11390-014-1428-7openalex-snapshot
MIMS: Towards a Message Interface Based Memory System
inferred← citeshttps://doi.org/10.1109/dsn.2014.32openalex-snapshot
Mitigating Write Disturbance in Super-Dense Phase Change Memories
inferred← citeshttps://doi.org/10.1109/hpca.2012.6169027openalex-snapshot
Improving write operations in MLC phase change memory
inferred← citeshttps://doi.org/10.1109/hpca.2018.00043openalex-snapshot
D-ORAM: Path-ORAM Delegation for Low Execution Interference on Cloud Servers with Untrusted Memory
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00031openalex-snapshot
Mitigating Voltage Drop in Resistive Memories by Dynamic RESET Voltage Regulation and Partition RESET
inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00047openalex-snapshot
AsyncDIMM: Achieving Asynchronous Execution in DIMM-Based Near-Memory Processing
inferred← citeshttps://doi.org/10.1109/iccd.2015.7357178openalex-snapshot
TriState-SET: Proactive SET for improved performance of MLC phase change memories
inferred← citeshttps://doi.org/10.1109/iccd53106.2021.00076openalex-snapshot
POMI: Polling-Based Memory Interface for Hybrid Memory System
inferred← citeshttps://doi.org/10.1109/isca.2014.6853194openalex-snapshot
A low power and reliable charge pump design for Phase Change Memories
inferred← citeshttps://doi.org/10.1109/isca.2014.6853228openalex-snapshot
Reducing access latency of MLC PCMs through line striping
inferred← citeshttps://doi.org/10.1109/islped.2013.6629297openalex-snapshot
WoM-SET: Low power proactive-SET-based PCM write using WoM code
inferred← citeshttps://doi.org/10.1109/isqed.2017.7918293openalex-snapshot
Constructing fast and energy efficient 1TnR based ReRAM crossbar memory
inferred← citeshttps://doi.org/10.1109/micro.2012.10openalex-snapshot
FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00074openalex-snapshot
Self-Managing DRAM: A Low-Cost Framework for Enabling Autonomous and Efficient DRAM Maintenance Operations
inferred← citeshttps://doi.org/10.1109/pact.2019.00030openalex-snapshot
FindeR: Accelerating FM-Index-Based Exact Pattern Matching in Genomic Sequences through ReRAM Technology
inferred← citeshttps://doi.org/10.1109/tpds.2017.2705125openalex-snapshot
HL-PCM: MLC PCM Main Memory with Accelerated Read
inferred← citeshttps://doi.org/10.1145/2678373.2665713openalex-snapshot
Reducing access latency of MLC PCMs through line striping
inferred← citeshttps://doi.org/10.1145/2678373.2665731openalex-snapshot
A low power and reliable charge pump design for phase change memories
inferred← citeshttps://doi.org/10.1145/2744769.2744841openalex-snapshot
Exploit imbalanced cell writes to mitigate write disturbance in dense phase change memory
inferred← citeshttps://doi.org/10.17760/d20291354openalex-snapshot
Architectural support for designing dependable non-volatile main memories
inferred← citeshttps://doi.org/10.48550/arxiv.1505.03476openalex-snapshot
Twin-Load: Building a Scalable Memory System over the Non-Scalable Interface
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