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FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4419-9551-3_2openalex-snapshot
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Non-volatile Memory
inferredcites →https://doi.org/10.1109/bmas.2006.283467openalex-snapshot
Macro-model of Spin-Transfer Torque based Magnetic Tunnel Junction device for hybrid Magnetic-CMOS design
inferredcites →https://doi.org/10.1109/dsn.2001.941433openalex-snapshot
The design and use of persistent memory on the DNCP hardware fault-tolerant platform
inferredcites →https://doi.org/10.1109/ftcs.1998.689484openalex-snapshot
Software exploitation of a fault-tolerant computer with a large memory
inferredcites →https://doi.org/10.1109/hpca.2010.5416658openalex-snapshot
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers
inferredcites →https://doi.org/10.1109/hpca.2013.6522311openalex-snapshot
Application-to-core mapping policies to reduce memory system interference in multi-core systems
inferredcites →https://doi.org/10.1109/hpca.2013.6522356openalex-snapshot
MISE: Providing performance predictability and improving fairness in shared main memory systems
inferredcites →https://doi.org/10.1109/hpca.2014.6835960openalex-snapshot
Reducing the cost of persistence for nonvolatile heaps in end user devices
inferredcites →https://doi.org/10.1109/iccd.2012.6378661openalex-snapshot
Row buffer locality aware caching policies for hybrid memories
inferredcites →https://doi.org/10.1109/iccd.2012.6378685openalex-snapshot
A case for small row buffers in non-volatile main memories
inferredcites →https://doi.org/10.1109/iccd.2013.6657033openalex-snapshot
LightTx: A lightweight transactional design in flash-based SSDs to support flexible transactions
inferredcites →https://doi.org/10.1109/iccd.2014.6974655openalex-snapshot
The Blacklisting Memory Scheduler: Achieving high performance and fairness at low cost
inferredcites →https://doi.org/10.1109/iccd.2014.6974684openalex-snapshot
Loose-Ordering Consistency for persistent memory
inferredcites →https://doi.org/10.1109/iedm.2004.1419329openalex-snapshot
Highly manufacturable high density phase change memory of 64Mb and beyond
inferredcites →https://doi.org/10.1109/iedm.2005.1609379openalex-snapshot
A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram
inferredcites →https://doi.org/10.1109/iedm.2010.5703395openalex-snapshot
Evidence and solution of over-RESET problem for HfOX based resistive memory with sub-ns switching speed and high endurance
inferredcites →https://doi.org/10.1109/iedm.2011.6131602openalex-snapshot
Extended scalability of perpendicular STT-MRAM towards sub-20nm MTJ node
inferredcites →https://doi.org/10.1109/iirw.2012.6468904openalex-snapshot
Reliability of low current filamentary HfO2 RRAM discussed in the framework of the hourglass SET/RESET model
inferredcites →https://doi.org/10.1109/imw.2013.6582086openalex-snapshot
Device performance in a fully functional 800MHz DDR3 spin torque magnetic random access memory
inferredcites →https://doi.org/10.1109/isca.2008.21openalex-snapshot
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach
inferredcites →https://doi.org/10.1109/isca.2008.7openalex-snapshot
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
inferredcites →https://doi.org/10.1109/isca.2012.6237032openalex-snapshot
A case for exploiting subarray-level parallelism (SALP) in DRAM
inferredcites →https://doi.org/10.1109/isca.2012.6237036openalex-snapshot
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems
inferredcites →https://doi.org/10.1109/ispass.2013.6557148openalex-snapshot
McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling
inferredcites →https://doi.org/10.1109/ispass.2013.6557176openalex-snapshot
Evaluating STT-RAM as an energy-efficient main memory alternative
inferredcites →https://doi.org/10.1109/isscc.2011.5746286openalex-snapshot
A 4Mb conductive-bridge resistive memory with 2.3GB/s read-throughput and 216MB/s program-throughput
inferredcites →https://doi.org/10.1109/isscc.2012.6176872openalex-snapshot
A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth
inferredcites →https://doi.org/10.1109/l-ca.2010.2openalex-snapshot
A Phase Change Memory as a Secure Main Memory
inferredcites →https://doi.org/10.1109/l-ca.2011.1openalex-snapshot
Fairness Metrics for Multi-Threaded Processors
inferredcites →https://doi.org/10.1109/l-ca.2012.2openalex-snapshot
Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management
inferredcites →https://doi.org/10.1109/mc.2013.189openalex-snapshot
How Persistent Memory Will Change Software Systems
inferredcites →https://doi.org/10.1109/micro.2004.22openalex-snapshot
Memory Controller Optimizations for Web Servers
inferredcites →https://doi.org/10.1109/micro.2007.21openalex-snapshot
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors
inferredcites →https://doi.org/10.1109/micro.2007.40openalex-snapshot
Process Variation Tolerant 3T1D-Based Cache Architectures
inferredcites →https://doi.org/10.1109/micro.2008.4771791openalex-snapshot
Prefetch-Aware DRAM Controllers
inferredcites →https://doi.org/10.1109/micro.2010.51openalex-snapshot
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
inferredcites →https://doi.org/10.1109/micro.2012.12openalex-snapshot
Transactional Memory Architecture and Implementation for IBM System Z
inferredcites →https://doi.org/10.1109/mm.2008.44openalex-snapshot
System-Level Performance Metrics for Multiprogram Workloads
inferredcites →https://doi.org/10.1109/mm.2010.24openalex-snapshot
Phase-Change Technology and the Future of Main Memory
inferredcites →https://doi.org/10.1109/sc.2010.50openalex-snapshot
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support
inferredcites →https://doi.org/10.1109/tcad.2012.2185930openalex-snapshot
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory
inferredcites →https://doi.org/10.1145/1394608.1382128openalex-snapshot
Parallelism-Aware Batch Scheduling
inferredcites →https://doi.org/10.1145/1394608.1382172openalex-snapshot
Self-Optimizing Memory Controllers
inferredcites →https://doi.org/10.1145/1400751.1400799openalex-snapshot
Distributed order scheduling and its application to multi-core dram controllers
inferredcites →https://doi.org/10.1145/1555754.1555758openalex-snapshot
Architecting phase change memory as a scalable dram alternative
inferredcites →https://doi.org/10.1145/1555754.1555759openalex-snapshot
A durable and energy efficient main memory using phase change memory technology
inferredcites →https://doi.org/10.1145/1555754.1555760openalex-snapshot
Scalable high performance main memory system using phase-change memory technology
inferredcites →https://doi.org/10.1145/1629575.1629589openalex-snapshot
Better I/O through byte-addressable, persistent memory
inferredcites →https://doi.org/10.1145/1669112.1669117openalex-snapshot
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
inferredcites →https://doi.org/10.1145/1669112.1669150openalex-snapshot
Application-aware prioritization mechanisms for on-chip networks
inferredcites →https://doi.org/10.1145/1669112.1669155openalex-snapshot
Improving memory bank-level parallelism in the presence of prefetching
inferredcites →https://doi.org/10.1145/1735970.1736023openalex-snapshot
Dynamically replicated memory
inferredcites →https://doi.org/10.1145/1736020.1736023openalex-snapshot
Dynamically replicated memory
inferredcites →https://doi.org/10.1145/1785414.1785441openalex-snapshot
Phase change memory architecture and the quest for scalability
inferredcites →https://doi.org/10.1145/1995896.1995911openalex-snapshot
Page placement in hybrid memory systems
inferredcites →https://doi.org/10.1145/2000064.2000081openalex-snapshot
Prefetch-aware shared resource management for multi-core systems
inferredcites →https://doi.org/10.1145/2155620.2155663openalex-snapshot
Parallel application memory scheduling
inferredcites →https://doi.org/10.1145/2155620.2155664openalex-snapshot
Reducing memory interference in multicore systems via application-aware memory channel partitioning
inferredcites →https://doi.org/10.1145/2366231.2337202openalex-snapshot
A case for exploiting subarray-level parallelism (SALP) in DRAM
inferredcites →https://doi.org/10.1145/2451116.2451137openalex-snapshot
Regularities considered harmful
inferredcites →https://doi.org/10.1145/2524211.2524216openalex-snapshot
Consistent, durable, and safe memory management for byte-addressable non volatile main memory
inferredcites →https://doi.org/10.1145/356989.357011openalex-snapshot
Symbiotic jobscheduling for a simultaneous mutlithreading processor
inferredcites →https://doi.org/10.1145/378993.379244openalex-snapshot
Symbiotic jobscheduling for a simultaneous multithreaded processor
inferredcites →https://doi.org/10.1147/rd.524.0465openalex-snapshot
Phase-change random access memory: A scalable technology
inferredcites →https://doi.org/10.1184/r1/6468164openalex-snapshot
A Case for Efficient Hardware/Software Cooperative Management of Storage and Memory
inferredcites →https://doi.org/10.1184/r1/6468701openalex-snapshot
DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems
inferredcites →https://doi.org/10.14778/2732228.2732231openalex-snapshot
Storage management in the NVRAM era
inferredcites →https://doi.org/10.5555/1960475.1960480openalex-snapshot
Consistent and durable data structures for non-volatile byte-addressable memory
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-319-90385-9_5openalex-snapshot
The Processing-in-Memory Paradigm: Mechanisms to Enable Adoption
inferred← citeshttps://doi.org/10.1016/bs.adcom.2017.04.004openalex-snapshot
Simple Operations in Memory to Reduce Data Movement
inferred← citeshttps://doi.org/10.1016/j.future.2017.12.033openalex-snapshot
In-memory big data analytics under space constraints using dynamic programming
inferred← citeshttps://doi.org/10.1016/j.future.2020.01.047openalex-snapshot
A pure hardware-driven scheduler for enhancing bank-level parallelism in a persistent memory controller
inferred← citeshttps://doi.org/10.1109/bigdata.2016.7840923openalex-snapshot
Container-based virtualization for byte-addressable NVM data storage
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446055openalex-snapshot
Atomic persistence for SCM with a non-intrusive backend controller
inferred← citeshttps://doi.org/10.1109/hpca.2017.50openalex-snapshot
ATOM: Atomic Durability in Non-volatile Memory through Hardware Logging
inferred← citeshttps://doi.org/10.1109/hpca.2018.00037openalex-snapshot
Steal but No Force: Efficient Hardware Undo+Redo Logging for Persistent Memory Systems
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00048openalex-snapshot
NVDIMM-C: A Byte-Addressable Non-Volatile Memory Module for Compatibility with Standard DDR Memory Interfaces
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00087openalex-snapshot
DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators
inferred← citeshttps://doi.org/10.1109/iccd.2016.7753327openalex-snapshot
A model for Application Slowdown Estimation in on-chip networks and its use for improving system fairness and performance
inferred← citeshttps://doi.org/10.1109/icde65448.2025.00252openalex-snapshot
OMeGa: Boosting Large-scale Graph Embeddings with Heterogeneous Memory Processing
inferred← citeshttps://doi.org/10.1109/ipdps.2017.60openalex-snapshot
Language-Based Optimizations for Persistence on Nonvolatile Main Memory Systems
inferred← citeshttps://doi.org/10.1109/isca.2018.00035openalex-snapshot
Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache
inferred← citeshttps://doi.org/10.1109/isca.2018.00045openalex-snapshot
DHTM: Durable Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00019openalex-snapshot
COSM: A Cooperative Scheduling Framework for Concurrent PIM and CPU Execution on Mobile Devices
inferred← citeshttps://doi.org/10.1109/isvlsi.2019.00028openalex-snapshot
Investigating Fairness in Disaggregated Non-Volatile Memories
inferred← citeshttps://doi.org/10.1109/lca.2015.2443105openalex-snapshot
Non-Intrusive Persistence with a Backend NVM Controller
inferred← citeshttps://doi.org/10.1109/micro.2016.7783712openalex-snapshot
Bridging the I/O performance gap for big data workloads: A new NVDIMM-based approach
inferred← citeshttps://doi.org/10.1109/micro.2016.7783761openalex-snapshot
Delegated persist ordering
inferred← citeshttps://doi.org/10.1109/micro.2018.00043openalex-snapshot
Improving the Performance and Endurance of Encrypted Non-Volatile Main Memory through Deduplicating Writes
inferred← citeshttps://doi.org/10.1109/micro.2018.00047openalex-snapshot
Persistence Parallelism Optimization: A Holistic Approach from Memory Bus to RDMA Network
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00049openalex-snapshot
Characterizing and Modeling Non-Volatile Memory Systems
inferred← citeshttps://doi.org/10.1109/msst.2016.7897078openalex-snapshot
Fast and failure-consistent updates of application data in non-volatile main memory file system
inferred← citeshttps://doi.org/10.1109/nvmsa.2015.7304356openalex-snapshot
Leveraging nonvolatility for architecture design with emerging NVM
inferred← citeshttps://doi.org/10.1109/nvmsa56066.2022.00010openalex-snapshot
Efficient and Atomic-Durable Persistent Memory through In-PM Hybrid Logging
inferred← citeshttps://doi.org/10.1109/sc.2016.75openalex-snapshot
DCA: A DRAM-cache-Aware DRAM Controller
inferred← citeshttps://doi.org/10.1109/scw63240.2024.00138openalex-snapshot
ACID Support for Compute eXpress Link Memory Transactions
inferred← citeshttps://doi.org/10.1109/tbdata.2018.2865964openalex-snapshot
Improving Bank-Level Parallelism for In-Memory Checkpointing in Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/tc.2016.2617333openalex-snapshot
Refresh-Aware Write Recovery Memory Controller
inferred← citeshttps://doi.org/10.1109/tc.2018.2881137openalex-snapshot
Sparse-Insertion Write Cache to Mitigate Write Disturbance Errors in Phase Change Memory
inferred← citeshttps://doi.org/10.1109/tc.2019.2933826openalex-snapshot
Integration and Boost of a Read-Modify-Write Module in Phase Change Memory System
inferred← citeshttps://doi.org/10.1109/tcad.2016.2618881openalex-snapshot
vFlash: Virtualized Flash for Optimizing the I/O Performance in Mobile Devices
inferred← citeshttps://doi.org/10.1109/tcad.2020.2966482openalex-snapshot
Miss Penalty Aware Cache Replacement for Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/tcad.2020.3015925openalex-snapshot
CacheTree: Reducing Integrity Verification Overhead of Secure Nonvolatile Memories
inferred← citeshttps://doi.org/10.1109/tpds.2016.2526003openalex-snapshot
BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling
inferred← citeshttps://doi.org/10.1145/2830772.2830805openalex-snapshot
Efficient persist barriers for multicores
inferred← citeshttps://doi.org/10.1145/2835512.2835520openalex-snapshot
Rethinking Memory System Design (along with Interconnects)
inferred← citeshttps://doi.org/10.1145/2872362.2872381openalex-snapshot
High-Performance Transactions for Persistent Memories
inferred← citeshttps://doi.org/10.1145/2896377.2901468openalex-snapshot
Exploiting Core Criticality for Enhanced GPU Performance
inferred← citeshttps://doi.org/10.1145/2954680.2872381openalex-snapshot
High-Performance Transactions for Persistent Memories
inferred← citeshttps://doi.org/10.1145/2964791.2901468openalex-snapshot
Exploiting Core Criticality for Enhanced GPU Performance
inferred← citeshttps://doi.org/10.1145/2987550.2987551openalex-snapshot
A Case for Virtualizing Persistent Memory
inferred← citeshttps://doi.org/10.1145/2990299.2990300openalex-snapshot
Rethinking memory system design
inferred← citeshttps://doi.org/10.1145/3078505.3078590openalex-snapshot
Understanding Reduced-Voltage Operation in Modern DRAM Devices
inferred← citeshttps://doi.org/10.1145/3079079.3079092openalex-snapshot
Design and implementation of bandwidth-aware memory placement and migration policies for heterogeneous memory systems
inferred← citeshttps://doi.org/10.1145/3084447openalex-snapshot
Understanding Reduced-Voltage Operation in Modern DRAM Devices
inferred← citeshttps://doi.org/10.1145/3084690openalex-snapshot
Word- and Partition-Level Write Variation Reduction for Improving Non-Volatile Cache Lifetime
inferred← citeshttps://doi.org/10.1145/3092255.3092270openalex-snapshot
Continuous checkpointing of HTM transactions in NVM
inferred← citeshttps://doi.org/10.1145/3156685.3092270openalex-snapshot
Continuous checkpointing of HTM transactions in NVM
inferred← citeshttps://doi.org/10.1145/3180270.3180275openalex-snapshot
A Case for Scoped Persist Barriers in GPUs
inferred← citeshttps://doi.org/10.1145/3240302.3240305openalex-snapshot
Hardware transactional persistent memory
inferred← citeshttps://doi.org/10.1145/3240302.3240310openalex-snapshot
Design guidelines for high-performance SCM hierarchies
inferred← citeshttps://doi.org/10.1145/3309697.3331482openalex-snapshot
Demystifying Complex Workload-DRAM Interactions
inferred← citeshttps://doi.org/10.1145/3352460.3358266openalex-snapshot
Towards Efficient NVDIMM-based Heterogeneous Storage Hierarchy Management for Big Data Workloads
inferred← citeshttps://doi.org/10.1145/3358180openalex-snapshot
Enabling and Exploiting Partition-Level Parallelism (PALP) in Phase Change Memories
inferred← citeshttps://doi.org/10.1145/3366708openalex-snapshot
Demystifying Complex Workload-DRAM Interactions
inferred← citeshttps://doi.org/10.1145/3377149openalex-snapshot
Improving Memory Efficiency in Heterogeneous MPSoCs through Row-Buffer Locality-aware Forwarding
inferred← citeshttps://doi.org/10.1145/3381898.3397210openalex-snapshot
Improving phase change memory performance with data content aware access
inferred← citeshttps://doi.org/10.1145/3407947.3407967openalex-snapshot
Cache/Memory Coordinated Fair Scheduling for Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1145/3676641.3716027openalex-snapshot
Virtuoso: Enabling Fast and Accurate Virtual Memory Research via an Imitation-based Operating System Simulation Methodology
inferred← citeshttps://doi.org/10.1145/3767110.3767127openalex-snapshot
Hierarchical Framework for Multi-node Compute eXpress Link Memory Transactions
inferred← citeshttps://doi.org/10.1155/2022/9552517openalex-snapshot
PCM-2R: Accelerating MLC PCM Writes via Data Reshaping and Remapping
inferred← citeshttps://doi.org/10.1184/r1/6469403openalex-snapshot
The Blacklisting Memory Scheduler: Balancing Performance, Fairness and Complexity
inferred← citeshttps://doi.org/10.1184/r1/6469421openalex-snapshot
The Main Memory System: Challenges and Opportunities
inferred← citeshttps://doi.org/10.1184/r1/6723512openalex-snapshot
Techniques for Shared Resource Management in Systems with Throughput Processors
inferred← citeshttps://doi.org/10.1184/r1/6724127.v1openalex-snapshot
Understanding and Improving the Latency of DRAM-Based Memory Systems
inferred← citeshttps://doi.org/10.14529/jsfi140302openalex-snapshot
Research Problems and Opportunities in Memory Systems
inferred← citeshttps://doi.org/10.1556/606.2023.00780openalex-snapshot
Exploring fair scheduling aspects – Through final exam scheduling
inferred← citeshttps://doi.org/10.20381/ruor-24222openalex-snapshot
Fabrication of Carbon Nanotube Field Effect Transistor Using Dielectrophoresis and Its Application as Static Random Access Memory Bit Cell
inferred← citeshttps://doi.org/10.23919/date51398.2021.9474073openalex-snapshot
Intelligent Architectures for Intelligent Computing Systems
inferred← citeshttps://doi.org/10.24355/dbbs.084-202001281133-0openalex-snapshot
Systems Support for Emerging Memory Technologies
inferred← citeshttps://doi.org/10.3390/electronics13173492openalex-snapshot
Enhancing QoS in Multicore Systems with Heterogeneous Memory Configurations
inferred← citeshttps://doi.org/10.48550/arxiv.1603.08454openalex-snapshot
Adaptive-Latency DRAM (AL-DRAM)
inferred← citeshttps://doi.org/10.48550/arxiv.1605.06483openalex-snapshot
Simple DRAM and Virtual Memory Abstractions to Enable Highly Efficient Memory Systems
inferred← citeshttps://doi.org/10.48550/arxiv.1609.02067openalex-snapshot
Practical Data Compression for Modern Memory Hierarchies
inferred← citeshttps://doi.org/10.48550/arxiv.1610.09603openalex-snapshot
The Processing Using Memory Paradigm:In-DRAM Bulk Copy, Initialization, Bitwise AND and OR
inferred← citeshttps://doi.org/10.48550/arxiv.1802.00320openalex-snapshot
Enabling the Adoption of Processing-in-Memory: Challenges, Mechanisms, Future Research Directions
inferred← citeshttps://doi.org/10.48550/arxiv.1804.11038openalex-snapshot
Holistic Management of the GPGPU Memory Hierarchy to Manage Warp-level Latency Tolerance
inferred← citeshttps://doi.org/10.48550/arxiv.1804.11040openalex-snapshot
A Memory Controller with Row Buffer Locality Awareness for Hybrid Memory Systems
inferred← citeshttps://doi.org/10.48550/arxiv.1804.11043openalex-snapshot
High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems
inferred← citeshttps://doi.org/10.48550/arxiv.1805.01966openalex-snapshot
Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism
inferred← citeshttps://doi.org/10.48550/arxiv.1805.03047openalex-snapshot
Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins
inferred← citeshttps://doi.org/10.48550/arxiv.1805.03502openalex-snapshot
RowClone: Accelerating Data Movement and Initialization Using DRAM
inferred← citeshttps://doi.org/10.48550/arxiv.1805.05926openalex-snapshot
Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems
inferred← citeshttps://doi.org/10.48550/arxiv.1902.07609openalex-snapshot
Understanding the Interactions of Workloads and DRAM Types: A Comprehensive Experimental Study
inferred← citeshttps://doi.org/10.5555/3195638.3195649openalex-snapshot
Bridging the I/O performance gap for big data workloads: a new NVDIMM-based approach
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