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NoCGuard: A Reliable Network-on-Chip Router Architecture
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/spe.2796openalex-snapshot
An energy efficient and low overhead fault mitigation technique for internet of thing edge devices reliable on‐chip communication
inferredcites →https://doi.org/10.1007/s10836-013-5389-5openalex-snapshot
Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip
inferredcites →https://doi.org/10.1016/j.micpro.2016.04.009openalex-snapshot
A low-cost, fault-tolerant and high-performance router architecture for on-chip networks
inferredcites →https://doi.org/10.1016/j.vlsi.2016.10.016openalex-snapshot
A high performance reliable NoC router
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/40.782564openalex-snapshot
Design challenges of technology scaling
inferredcites →https://doi.org/10.1109/7298.946457openalex-snapshot
Hot carrier degradation and ESD in submicrometer CMOS technologies: how do they interact?
inferredcites →https://doi.org/10.1109/dft.2014.6962086openalex-snapshot
Rescuing healthy cores against disabled routers
inferredcites →https://doi.org/10.1109/dsd.2007.4341515openalex-snapshot
On network-on-chip comparison
inferredcites →https://doi.org/10.1109/dsn.2007.8openalex-snapshot
A Framework for Architecture-Level Lifetime Reliability Modeling
inferredcites →https://doi.org/10.1109/hkedm.1999.836404openalex-snapshot
On the oxide thickness dependence of the time-dependent-dielectric-breakdown
inferredcites →https://doi.org/10.1109/hpca.2001.903268openalex-snapshot
A delay model and speculative architecture for pipelined routers
inferredcites →https://doi.org/10.1109/hpca.2006.1598108openalex-snapshot
BulletProof: A Defect~Tolerant CMP Switch Architecture
inferredcites →https://doi.org/10.1109/icecs.2004.1399629openalex-snapshot
Electromigration-dependent parametric yield estimation
inferredcites →https://doi.org/10.1109/iedm.2004.1419079openalex-snapshot
Mechanism of negative bias temperature instability in CMOS devices degradation, recovery and impact of nitrogen
inferredcites →https://doi.org/10.1109/iedm.2007.4418976openalex-snapshot
Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS
inferredcites →https://doi.org/10.1109/ispass.2009.4919636openalex-snapshot
GARNET: A detailed on-chip network model inside a full-system simulator
inferredcites →https://doi.org/10.1109/jssc.1982.1051741openalex-snapshot
Alpha-Particle-Induced Soft Error Rate in VLSI Circuits
inferredcites →https://doi.org/10.1109/micro.2012.15openalex-snapshot
NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures
inferredcites →https://doi.org/10.1109/mm.2005.110openalex-snapshot
Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation
inferredcites →https://doi.org/10.1109/nas.2013.28openalex-snapshot
REPAIR: A Reliable Partial-Redundancy-Based Router in NoC
inferredcites →https://doi.org/10.1109/recosoc.2017.8016161openalex-snapshot
Fault-resilient NoC router with transparent resource allocation
inferredcites →https://doi.org/10.1109/t-ed.1979.19370openalex-snapshot
Alpha-particle-induced soft errors in dynamic memories
inferredcites →https://doi.org/10.1109/tc.2018.2865948openalex-snapshot
Efficient Design-for-Test Approach for Networks-on-Chip
inferredcites →https://doi.org/10.1109/te.1985.4321753openalex-snapshot
Probability & Statistics with Reliability, Queueing and Computer Science Applications-K. S. Trivedi
inferredcites →https://doi.org/10.1109/tetc.2016.2597799openalex-snapshot
An Energy-Efficient NoC Router with Adaptive Fault-Tolerance Using Channel Slicing and On-Demand TMR
inferredcites →https://doi.org/10.1109/tpds.2016.2521641openalex-snapshot
Shield: A Reliable Network-on-Chip Router Architecture for Chip Multiprocessors
inferredcites →https://doi.org/10.1109/tr.1963.5218202openalex-snapshot
Time to Failure and Availability of Paralleled Systems with Repair
inferredcites →https://doi.org/10.1109/tvlsi.2012.2204909openalex-snapshot
Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router
inferredcites →https://doi.org/10.1145/1028176.1006725openalex-snapshot
The Case for Lifetime Reliability-Aware Microprocessors
inferredcites →https://doi.org/10.1145/1150019.1136487openalex-snapshot
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
inferredcites →https://doi.org/10.1145/2522968.2522976openalex-snapshot
Methods for fault tolerance in networks-on-chip
inferredcites →https://doi.org/10.1145/2717764.2717783openalex-snapshot
Open Cell Library in 15nm FreePDK Technology
inferredcites →https://doi.org/10.1145/2886781openalex-snapshot
A Survey on Design Approaches to Circumvent Permanent Faults in Networks-on-Chip
inferredcites →https://doi.org/10.1147/rd.421.0117openalex-snapshot
Terrestrial cosmic ray intensities
inferredcites →https://doi.org/10.1147/rd.462.0287openalex-snapshot
CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics
inferredcites →https://doi.org/10.3390/jlpea9010011openalex-snapshot
Tolerating Permanent Faults in the Input Port of the Network on Chip Router
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11227-025-07733-6openalex-snapshot
Simultaneous optimization of network-on-chip to improve reliability and reduce average packet latency considering buffer size constraints
inferred← citeshttps://doi.org/10.1007/s11227-026-08726-9openalex-snapshot
CoST-HNoC: comprehensive SEU-tolerant routing for 1K-core hypercube NoC
inferred← citeshttps://doi.org/10.1007/s12046-025-02923-7openalex-snapshot
An efficient quasi-delay-insensitive (QDI)-based asynchronous NoC with fault tolerant features
inferred← citeshttps://doi.org/10.1007/s12626-024-00175-1openalex-snapshot
Internet of multimedia things (IoMT): A review
inferred← citeshttps://doi.org/10.1016/j.jnca.2021.103319openalex-snapshot
An efficient and cost effective application mapping for network-on-chip using Andean condor algorithm
inferred← citeshttps://doi.org/10.1049/cds2.12127openalex-snapshot
A novel buffering fault‐tolerance approach for network on chip (NoC)
inferred← citeshttps://doi.org/10.1108/cw-10-2020-0268openalex-snapshot
Adaptive hybrid arbiter design for real-time traffic-aware scheduling
inferred← citeshttps://doi.org/10.1109/access.2021.3120079openalex-snapshot
Application Mapping Using Cuckoo Search Optimization With Lévy Flight for NoC-Based System
inferred← citeshttps://doi.org/10.21203/rs.3.rs-4102834/v1openalex-snapshot
Simultaneous Optimization of Network-on-Chip for Improved Reliability and Reduced Average Packet Latency Considering Buffer Size Constraints
inferred← citeshttps://doi.org/10.32604/cmc.2021.012365openalex-snapshot
Design, Implementation and Verification of Topology Network Architecture of Smart Home Tree
inferred← citeshttps://doi.org/10.3390/electronics9111783openalex-snapshot
Savior: A Reliable Fault Resilient Router Architecture for Network-on-Chip
inferred← citeshttps://doi.org/10.3390/mi14020335openalex-snapshot
Approximate Priority Hybrid 3DNoC Buffered-Bufferless Router
inferred← citeshttps://doi.org/10.3390/s20082334openalex-snapshot
Internet of Multimedia Things (IoMT): Opportunities, Challenges and Solutions
inferred← citeshttps://doi.org/10.3390/s20185355openalex-snapshot
Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things
inferred← citeshttps://doi.org/10.3390/s21124219openalex-snapshot
Paraconsistent Annotated Logic Algorithms Applied in Management and Control of Communication Network Routes
inferred← citeshttps://doi.org/10.3390/s21155102openalex-snapshot
An Optimized Nature-Inspired Metaheuristic Algorithm for Application Mapping in 2D-NoC
inferred← citeshttps://doi.org/10.48084/etasr.17963openalex-snapshot
Boosting WLAN Performance Using a Hybrid Network-on-Chip Routing Architecture with Predictive Congestion Avoidance
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