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Predicting Performance Impact of DVFS for Realistic Memory Systems
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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A Detailed Study on Phase Predictors
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Runtime Performance Projection Model for Dynamic Power Management
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Fine-grained dynamic voltage and frequency scaling for precise energy and performance trade-off based on the ratio of off-chip access to on-chip computation times
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Energy efficient CMOS microprocessor design
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Phase Characterization for Power: Evaluating Control-Flow-Based and Event-Counter-Based Techniques
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System level analysis of fast, per-core DVFS using on-chip switching regulators
inferredcites →https://doi.org/10.1109/igcc.2011.6008552openalex-snapshot
Green governors: A framework for Continuously Adaptive DVFS
inferredcites →https://doi.org/10.1109/igcc.2011.6008553openalex-snapshot
Practical performance prediction under Dynamic Voltage Frequency Scaling
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Analytic evaluation of shared-memory systems with ILP processors
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Increasing processor performance by implementing deeper pipelines
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A first-order superscalar processor model
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A family of 45nm IA processors
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A Fully-Integrated 3-Level DC-DC Converter for Nanosecond-Scale DVFS
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The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best
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Theoretical modeling of superscalar processor performance
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A static power model for architects
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Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic Instrumentation
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Live, Runtime Phase Monitoring and Prediction on Real Systems with Application to Dynamic Power Management
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Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs
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Bulldozer: An Approach to Multithreaded Compute Performance
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Exploring instruction-fetch bandwidth requirement in wide-issue superscalar processors
inferredcites →https://doi.org/10.1109/tc.1987.1676981openalex-snapshot
Characterization of Branch and Data Dependencies in Programs for Evaluating Pipeline Performance
inferredcites →https://doi.org/10.1109/tc.2010.65openalex-snapshot
A Counter Architecture for Online DVFS Profitability Estimation
inferredcites →https://doi.org/10.1145/1028176.1006729openalex-snapshot
A First-Order Superscalar Processor Model
inferredcites →https://doi.org/10.1145/1044823.1044824openalex-snapshot
The optimum pipeline depth considering both power and performance
inferredcites →https://doi.org/10.1145/1077603.1077657openalex-snapshot
Power prediction for intel XScale® processors using performance monitoring unit events
inferredcites →https://doi.org/10.1145/1183401.1183426openalex-snapshot
Online power-performance adaptation of multithreaded programs using hardware event-based prediction
inferredcites →https://doi.org/10.1145/1283780.1283825openalex-snapshot
Dynamic voltage frequency scaling for multi-tasking systems using online learning
inferredcites →https://doi.org/10.1145/1454115.1454151openalex-snapshot
Prediction models for multi-dimensional power-performance optimization on many cores
inferredcites →https://doi.org/10.1145/1534909.1534910openalex-snapshot
A mechanistic performance model for superscalar out-of-order processors
inferredcites →https://doi.org/10.1145/1787275.1787336openalex-snapshot
Applying statistical machine learning to multicore voltage & frequency scaling
inferredcites →https://doi.org/10.1145/1787275.1787338openalex-snapshot
Interval-based models for run-time DVFS orchestration in superscalar processors
inferredcites →https://doi.org/10.1145/192724.192730openalex-snapshot
Theoretical modeling of superscalar processor performance
inferredcites →https://doi.org/10.1145/1998582.1998590openalex-snapshot
Memory power management via dynamic voltage/frequency scaling
inferredcites →https://doi.org/10.1145/279358.279408openalex-snapshot
Analytic evaluation of shared-memory systems with ILP processors
inferredcites →https://doi.org/10.1145/360128.360148openalex-snapshot
A static power model for architects
inferredcites →https://doi.org/10.1145/545214.545219openalex-snapshot
Increasing processor performance by implementing deeper pipelines
inferredcites →https://doi.org/10.5555/520793.825746openalex-snapshot
Exploring instruction-fetch bandwidth requirement in wide-issue superscalar processors
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Event-based scheduling for energy-efficient QoS (eQoS) in mobile Web applications
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DVFS for NoCs in CMPs: A thread voting approach
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μDPM: Dynamic Power Management for the Microsecond Era
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Dynamic WCET Estimation for Real-Time Multicore Embedded Systems Supporting DVFS
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Do Radiation and Aging Impact DVFS? TCAD-based Analysis on 22 nm FDSOI Latches
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SCALABLE DYNAMIC MULTI-RESOURCE ALLOCATION IN MULTICORE SYSTEMS
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