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PMU-Events-Driven DVFS Techniques for Improving Energy Efficiency of Modern Processors
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/cpe.6580openalex-snapshot
duf : Dynamic uncore frequency scaling to reduce power consumption
inferredcites →https://doi.org/10.1007/978-1-4302-6638-9openalex-snapshot
Energy Efficient Servers: Blueprints for Data Center Optimization
inferredcites →https://doi.org/10.1007/978-3-642-23400-2_9openalex-snapshot
Reducing Energy Usage with Memory and Computation-Aware Dynamic Frequency Scaling
inferredcites →https://doi.org/10.1007/978-3-642-55224-3_74openalex-snapshot
The Energy/Frequency Convexity Rule: Modeling and Experimental Validation on Mobile Devices
inferredcites →https://doi.org/10.1016/j.apenergy.2021.116798openalex-snapshot
Usage impact on data center electricity needs: A system dynamic forecasting model
inferredcites →https://doi.org/10.1016/j.suscom.2017.10.015openalex-snapshot
Performance and energy metrics for multi-threaded applications on DVFS processors
inferredcites →https://doi.org/10.1016/j.suscom.2017.12.002openalex-snapshot
Modeling of the CPU frequency to minimize energy consumption in parallel applications
inferredcites →https://doi.org/10.1016/j.suscom.2019.01.022openalex-snapshot
Model-based optimization of the energy efficiency of multi-threaded applications
inferredcites →https://doi.org/10.1109/apec.2014.6803344openalex-snapshot
FIVR — Fully integrated voltage regulators on 4th generation Intel® Core™ SoCs
inferredcites →https://doi.org/10.1109/e2sc.2016.015openalex-snapshot
Software Controlled Clock Modulation for Energy Efficiency Optimization on Intel Processors
inferredcites →https://doi.org/10.1109/hotchips.2012.7476478openalex-snapshot
Power management of the third generation intel core micro architecture formerly codenamed ivy bridge
inferredcites →https://doi.org/10.1109/hpca.2002.995696openalex-snapshot
Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling
inferredcites →https://doi.org/10.1109/hpca.2014.6835969openalex-snapshot
Dynamic management of TurboMode in modern multi-core chips
inferredcites →https://doi.org/10.1109/hpcs48598.2019.9188239openalex-snapshot
Energy Efficiency Features of the Intel Skylake-SP Processor and Their Impact on Performance
inferredcites →https://doi.org/10.1109/iccad.2002.1167562openalex-snapshot
Power efficiency of voltage scaling in multiple clock multiple voltage cores
inferredcites →https://doi.org/10.1109/iccad.2006.320116openalex-snapshot
Dynamic Voltage and Frequency Management Based on Variable Update Intervals for Frequency Setting
inferredcites →https://doi.org/10.1109/icghpc.2016.7508065openalex-snapshot
Adaptive Power Management for HPC applications
inferredcites →https://doi.org/10.1109/icppw.2010.38openalex-snapshot
LIKWID: A Lightweight Performance-Oriented Tool Suite for x86 Multicore Environments
inferredcites →https://doi.org/10.1109/icppw.2012.39openalex-snapshot
Measuring Energy and Power with PAPI
inferredcites →https://doi.org/10.1109/igcc.2011.6008552openalex-snapshot
Green governors: A framework for Continuously Adaptive DVFS
inferredcites →https://doi.org/10.1109/iiswc.2009.5306782openalex-snapshot
Evaluation of the Intel® Core™ i7 Turbo Boost feature
inferredcites →https://doi.org/10.1109/iiswc50251.2020.00019openalex-snapshot
CPI for Runtime Performance Measurement: The Good, the Bad, and the Ugly
inferredcites →https://doi.org/10.1109/ipdps.2016.118openalex-snapshot
A Methodology for Modeling Dynamic and Static Power Consumption for Multicore Processors
inferredcites →https://doi.org/10.1109/ipdpsw.2015.144openalex-snapshot
Using Dynamic Duty Cycle Modulation to Improve Energy Efficiency in High Performance Computing
inferredcites →https://doi.org/10.1109/ipdpsw.2015.70openalex-snapshot
An Energy Efficiency Feature Survey of the Intel Haswell Processor
inferredcites →https://doi.org/10.1109/ispass.2014.6844459openalex-snapshot
A Top-Down method for performance analysis and counters architecture
inferredcites →https://doi.org/10.1109/micro.2003.1253186openalex-snapshot
Runtime power monitoring in high-end processors: methodology and empirical data
inferredcites →https://doi.org/10.1109/micro.2012.23openalex-snapshot
Predicting Performance Impact of DVFS for Realistic Memory Systems
inferredcites →https://doi.org/10.1109/mm.2006.73openalex-snapshot
IPC Considered Harmful for Multiprocessor Workloads
inferredcites →https://doi.org/10.1109/mm.2012.12openalex-snapshot
Power-Management Architecture of the Intel Microarchitecture Code-Named Sandy Bridge
inferredcites →https://doi.org/10.1109/mm.2012.20openalex-snapshot
What is Happening to Power, Performance, and Software?
inferredcites →https://doi.org/10.1109/mm.2017.38openalex-snapshot
Inside 6th-Generation Intel Core: New Microarchitecture Code-Named Skylake
inferredcites →https://doi.org/10.1109/pdp.2015.73openalex-snapshot
DVFS Governor for HPC: Higher, Faster, Greener
inferredcites →https://doi.org/10.1109/sc.companion.2012.94openalex-snapshot
Energy-Centric DVFS Controling Method for Multi-core Platforms
inferredcites →https://doi.org/10.1109/southeastcon42311.2019.9020474openalex-snapshot
Battle of Compilers: An Experimental Evaluation Using SPEC CPU2017
inferredcites →https://doi.org/10.1109/southeastcon42311.2019.9020637openalex-snapshot
Impact of Thread and Frequency Scaling on Performance and Energy Efficiency: An Evaluation of Core i7-8700K Using SPEC CPU2017
inferredcites →https://doi.org/10.1109/tcad.2012.2235126openalex-snapshot
Accurate Modeling of the Delay and Energy Overhead of Dynamic Voltage and Frequency Scaling in Modern Microprocessors
inferredcites →https://doi.org/10.1109/tpds.2020.3004383openalex-snapshot
Dynamic Undervolting to Improve Energy Efficiency on Multicore X86 CPUs
inferredcites →https://doi.org/10.1109/vlsi-soc.2019.8920389openalex-snapshot
The Impact of Turbo Frequency on the Energy, Performance, and Aging of Parallel Applications
inferredcites →https://doi.org/10.1109/vlsi.2008.98openalex-snapshot
Continuous Frequency Adjustment Technique Based on Dynamic Workload Prediction
inferredcites →https://doi.org/10.1145/1454115.1454151openalex-snapshot
Prediction models for multi-dimensional power-performance optimization on many cores
inferredcites →https://doi.org/10.2172/1407078openalex-snapshot
Roofline: An Insightful Visual Performance Model for Floating-Point Programs and Multicore Architectures
inferredcites →https://doi.org/10.3390/challe6010117openalex-snapshot
On Global Electricity Usage of Communication Technology: Trends to 2030
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-981-95-9846-5_4openalex-snapshot
Energy-Aware Optimization of CFD Workloads in HPC via Machine Learning-Based Dynamic CPU Scaling
inferred← citeshttps://doi.org/10.1016/j.sysarc.2026.103980openalex-snapshot
PMC-assisted runtime workload-aware power-state adaptation using OS-level actuation
inferred← citeshttps://doi.org/10.1109/aiei69164.2026.11496728openalex-snapshot
A Lightweight Hybrid DVFS Governor with EMA Smoothing and Asymmetric Hysteresis: FPGA Based Evaluation and Node-Scaled Analysis
inferred← citeshttps://doi.org/10.1109/ccgrid59990.2024.00039openalex-snapshot
Is the powersave governor really saving power?
inferred← citeshttps://doi.org/10.1109/eitce70137.2026.11634365openalex-snapshot
Optimizing CPU DVFS Using ARM AMU Memory Stall Events
inferred← citeshttps://doi.org/10.1109/ic2pct68894.2026.11584401openalex-snapshot
Power-Efficient VLSI Design in Advanced Technology Nodes
inferred← citeshttps://doi.org/10.1109/icecs202256217.2022.9971023openalex-snapshot
DVFS method of memory hierarchy based on CPU microarchitectural information
inferred← citeshttps://doi.org/10.1109/icept71373.2026.11690353openalex-snapshot
Runtime Power Map Prediction of Multicore Processors Driven by Performance Semantics
inferred← citeshttps://doi.org/10.1109/jsen.2025.3558221openalex-snapshot
A Spatiotemporal Correlation-Based Low-Power Task Scheduling and Anomaly Detection for HM-FW Sensing Systems
inferred← citeshttps://doi.org/10.1109/mobilecloud66020.2025.00014openalex-snapshot
THEAS: Efficient Power Management in Multi-Core CPUs via Cache-Aware Resource Scheduling
inferred← citeshttps://doi.org/10.1109/tcad.2024.3360319openalex-snapshot
OS-Level PMC-Based Runtime Thermal Control for ARM Mobile CPUs
inferred← citeshttps://doi.org/10.1145/3679240.3734588openalex-snapshot
Revisiting CPU Performance Scaling for Energy-Efficient Packet Processing Applications
inferred← citeshttps://doi.org/10.1145/3778358openalex-snapshot
SpiderSense: Lightweight Last-Level Cache Management via Time Period Tagging for LLC-Critical Workloads
inferred← citeshttps://doi.org/10.54097/pkgmn637openalex-snapshot
Neural Methods for Adaptive Voltage and Frequency Scaling in Energy Aware Processors
inferred← citeshttps://doi.org/10.56830/ijsie202401openalex-snapshot
Addressing power efficiency challenges in AI hardware through verification
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