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NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/j.1538-7305.1953.tb01433.xopenalex-snapshot
A Study of Non-Blocking Switching Networks
inferredcites →https://doi.org/10.1002/j.1538-7305.1964.tb04103.xopenalex-snapshot
Optimal Rearrangeable Multistage Connecting Networks
inferredcites →https://doi.org/10.1109/12.83652openalex-snapshot
Express cubes: improving the performance of k-ary n-cube interconnection networks
inferredcites →https://doi.org/10.1109/ectc.2007.373805openalex-snapshot
Analysis of the Induced Stresses in Silicon During Thermcompression Cu-Cu Bonding of Cu-Through-Vias in 3D-SIC Architecture
inferredcites →https://doi.org/10.1109/hpca.2009.4798234openalex-snapshot
A low-radix and low-diameter 3D interconnection network design
inferredcites →https://doi.org/10.1109/hpca.2009.4798251openalex-snapshot
Express Cube Topologies for on-Chip Interconnects
inferredcites →https://doi.org/10.1109/iccad.2010.5654245openalex-snapshot
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study
inferredcites →https://doi.org/10.1109/iccd.2012.6378672openalex-snapshot
3D-NoC: Reconfigurable 3D photonic on-chip interconnect for multicores
inferredcites →https://doi.org/10.1109/isca.2008.13openalex-snapshot
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
inferredcites →https://doi.org/10.1109/isca.2008.15openalex-snapshot
3D-Stacked Memory Architectures for Multi-core Processors
inferredcites →https://doi.org/10.1109/ispass.2013.6557149openalex-snapshot
A detailed and flexible cycle-accurate Network-on-Chip simulator
inferredcites →https://doi.org/10.1109/isqed.2006.77openalex-snapshot
Interconnect and thermal-aware floorplanning for 3D microprocessors
inferredcites →https://doi.org/10.1109/jssc.2011.2164731openalex-snapshot
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 $\times$ 128 I/Os Using TSV Based Stacking
inferredcites →https://doi.org/10.1109/mdt.2005.134openalex-snapshot
Bridging the Processor-Memory Performance Gapwith 3D IC Technology
inferredcites →https://doi.org/10.1109/micro.2006.18openalex-snapshot
Die Stacking (3D) Microarchitecture
inferredcites →https://doi.org/10.1109/micro.2007.15openalex-snapshot
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
inferredcites →https://doi.org/10.1109/micro.2007.29openalex-snapshot
Flattened Butterfly Topology for On-Chip Networks
inferredcites →https://doi.org/10.1109/micro.2010.18openalex-snapshot
Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs
inferredcites →https://doi.org/10.1109/micro.2010.50openalex-snapshot
Throughput-Effective On-Chip Networks for Manycore Accelerators
inferredcites →https://doi.org/10.1109/micro.2012.25openalex-snapshot
NOC-Out: Microarchitecting a Scale-Out Processor
inferredcites →https://doi.org/10.1109/mm.2007.4378780openalex-snapshot
On-Chip Interconnection Architecture of the Tile Processor
inferredcites →https://doi.org/10.1109/newcas.2010.5603776openalex-snapshot
Highly-scalable 3D CLOS NOC for many-core CMPs
inferredcites →https://doi.org/10.1109/nocs.2012.15openalex-snapshot
CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers
inferredcites →https://doi.org/10.1109/nocs.2012.31openalex-snapshot
DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling
inferredcites →https://doi.org/10.1109/pact.2013.6618805openalex-snapshot
Memory-centric system interconnect design with hybrid memory cubes
inferredcites →https://doi.org/10.1109/pact.2013.6618812openalex-snapshot
Memory-centric system interconnect design with Hybrid Memory Cubes
inferredcites →https://doi.org/10.1109/sc.2010.50openalex-snapshot
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support
inferredcites →https://doi.org/10.1109/tc.1985.6312192openalex-snapshot
Fat-trees: Universal networks for hardware-efficient supercomputing
inferredcites →https://doi.org/10.1145/1080695.1070005openalex-snapshot
Microarchitecture of a High-Radix Router
inferredcites →https://doi.org/10.1145/1120725.1120787openalex-snapshot
Thermal-driven multilevel routing for 3-D ICs
inferredcites →https://doi.org/10.1145/1127908.1127915openalex-snapshot
Thermal analysis of a 3D die-stacked high-performance microprocessor
inferredcites →https://doi.org/10.1145/1146909.1147160openalex-snapshot
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
inferredcites →https://doi.org/10.1145/1148015.1148016openalex-snapshot
Design space exploration for 3D architectures
inferredcites →https://doi.org/10.1145/1150019.1136497openalex-snapshot
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
inferredcites →https://doi.org/10.1145/1183401.1183430openalex-snapshot
Design tradeoffs for tiled CMP on-chip networks
inferredcites →https://doi.org/10.1145/1250662.1250680openalex-snapshot
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
inferredcites →https://doi.org/10.1145/1250662.1250693openalex-snapshot
Architectural implications of brick and mortar silicon manufacturing
inferredcites →https://doi.org/10.1145/1273440.1250693openalex-snapshot
Architectural implications of brick and mortar silicon manufacturing
inferredcites →https://doi.org/10.1145/1394608.1382159openalex-snapshot
3D-Stacked Memory Architectures for Multi-core Processors
inferredcites →https://doi.org/10.1145/1555754.1555810openalex-snapshot
Achieving predictable performance through better memory controller placement in many-core CMPs
inferredcites →https://doi.org/10.1145/1837274.1837315openalex-snapshot
Virtual channels vs. multiple physical networks
inferredcites →https://doi.org/10.1145/369691.369763openalex-snapshot
Interconnect characteristics of 2.5-D system integration scheme
inferredcites →https://doi.org/10.5555/2133429.2133571openalex-snapshot
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Design of time‐interleaved data acquisition system based on Network on Chip
inferred← citeshttps://doi.org/10.1002/ett.3747openalex-snapshot
An expandable topology with low wiring congestion for silicon interposer‐based network‐on‐chip systems
inferred← citeshttps://doi.org/10.1007/978-981-10-2209-8_4openalex-snapshot
Overcoming and Analyzing the Bottleneck of Interposer Network in 2.5D NoC Architecture
inferred← citeshttps://doi.org/10.1007/978-981-15-7090-2_13openalex-snapshot
Fundamentals of Heat Dissipation in 3D IC Packaging and Thermal-Aware Design
inferred← citeshttps://doi.org/10.1007/s11227-019-02964-wopenalex-snapshot
Decreasing latency considering power consumption issue in silicon interposer-based network-on-chip
inferred← citeshttps://doi.org/10.1007/s11432-023-3926-8openalex-snapshot
Review of chiplet-based design: system architecture and interconnection
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Survey on chiplets: interface, interconnect and integration methodology
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Topology Specialization for Networks-on-Chip in the Dark Silicon Era
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A one-to-many traffic-oriented mm-wave wireless network-in-package interconnection architecture for multichip computing systems
inferred← citeshttps://doi.org/10.1016/j.sysarc.2019.07.003openalex-snapshot
CLBM: Controlled load-balancing mechanism for congestion management in silicon interposer NoC architecture
inferred← citeshttps://doi.org/10.1038/s44335-026-00078-0openalex-snapshot
Metallic toxicity as a consideration for future computing paradigms
inferred← citeshttps://doi.org/10.1088/2399-6528/ac4dd5openalex-snapshot
Roadmap for machine learning based network-on-chip (M/L NoC) technology and its analysis for researchers
inferred← citeshttps://doi.org/10.1109/asp-dac58780.2024.10473888openalex-snapshot
Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration
inferred← citeshttps://doi.org/10.1109/cads.2017.8310676openalex-snapshot
NoD: Network-on-Die as a standalone NoC for heterogeneous many-core systems in 2.5D ICs
inferred← citeshttps://doi.org/10.1109/cicc63670.2025.10983802openalex-snapshot
A High-Performance Passive Base System for Distributed AI/Media Acceleration
inferred← citeshttps://doi.org/10.1109/dac18072.2020.9218654openalex-snapshot
A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures
inferred← citeshttps://doi.org/10.1109/ddecs.2017.7934565openalex-snapshot
From online fault detection to fault management in Network-on-Chips: A ground-up approach
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446076openalex-snapshot
The runahead network-on-chip
inferred← citeshttps://doi.org/10.1109/hpca.2018.00047openalex-snapshot
A Case for Packageless Processors
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00043openalex-snapshot
EquiNox: Equivalent NoC Injection Routers for Silicon Interposer-Based Throughput Processors
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00069openalex-snapshot
Enhancing Collective Communication in MCM Accelerators for Deep Learning Training
inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00117openalex-snapshot
EIGEN: Enabling Efficient 3DIC Interconnect with Heterogeneous Dual-Layer Network-on-Active-Interposer
inferred← citeshttps://doi.org/10.1109/hpcs.2017.81openalex-snapshot
Efficient Data-Driven Task Allocation for Future Many-Cluster On-chip Systems
inferred← citeshttps://doi.org/10.1109/iccad.2017.8203849openalex-snapshot
Cost-effective design of scalable high-performance systems using active and passive interposers
inferred← citeshttps://doi.org/10.1109/iccd.2016.7753258openalex-snapshot
Scalable memory fabric for silicon interposer-based multi-core systems
inferred← citeshttps://doi.org/10.1109/iccd.2016.7753352openalex-snapshot
DLL: A dynamic latency-aware load-balancing strategy in 2.5D NoC architecture
inferred← citeshttps://doi.org/10.1109/iccs56666.2022.9936469openalex-snapshot
Fast Turn Restriction Algorithm to Build Deadlock-Free Modular Chiplet Integration Systems
inferred← citeshttps://doi.org/10.1109/igcc.2017.8323583openalex-snapshot
Increasing interposer utilization: A scalable, energy efficient and high bandwidth multicore-multichip integration solution
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An Asymmetric, Energy Efficient One-to-Many Traffic-Aware Wireless Network-in-Package Interconnection Architecture for Multichip Systems
inferred← citeshttps://doi.org/10.1109/ipdps47924.2020.00012openalex-snapshot
Neksus: An Interconnect for Heterogeneous System-In-Package Architectures
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Modular Routing Design for Chiplet-Based Systems
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00119openalex-snapshot
Omelet: A Packaging-Aware Hierarchical Interconnect Simulator for 2.5D/3D Chiplet Architectures
inferred← citeshttps://doi.org/10.1109/iscas48785.2022.9937877openalex-snapshot
Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer
inferred← citeshttps://doi.org/10.1109/islped.2019.8824957openalex-snapshot
Robust Low Power Clock Synchronization for Multi-Die Systems
inferred← citeshttps://doi.org/10.1109/ispass64960.2025.00050openalex-snapshot
Library of Networks: An Online Tool for Design and Analysis of Network Topologies
inferred← citeshttps://doi.org/10.1109/mcas.2024.3359571openalex-snapshot
Chiplet-GAN: Chiplet-Based Accelerator Design for Scalable Generative Adversarial Network Inference [Feature]
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Survey of Network-on-Chip (NoC) for Heterogeneous Multicore Systems
inferred← citeshttps://doi.org/10.1109/mcsoc67473.2025.00030openalex-snapshot
Hybrid Interconnect and Intermediate Memory-Based 2.5D NoC Architecture for High Performance Computing Applications
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Locality-Centric Data and Threadblock Management for Massive GPUs
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CPElide: Efficient Multi-Chiplet GPU Implicit Synchronization
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Achieving Exascale Capabilities through Heterogeneous Computing
inferred← citeshttps://doi.org/10.1109/mwscas48704.2020.9184704openalex-snapshot
7-mm low-latency inter-chiplet serial link with silicon interposer
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InC2: Design of Interconnection Systems for Composable Chiplet Architectures
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Towards Energy-Efficient High-Throughput Photonic NoCs for 2.5D Integrated Systems: A Case for AWGRs
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Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems
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SID-Mesh: Diagonal Mesh Topology for Silicon Interposer in 2.5D NoC with Introducing a New Routing Algorithm
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Energy-efficient wireless interconnection framework for multichip systems with in-package memory stacks
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A One-to-Many Traffic Aware Wireless Network-in-Package for Multi-Chip Computing Platforms
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MViD: Sparse Matrix-Vector Multiplication in Mobile DRAM for Accelerating Recurrent Neural Networks
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Remote Control: A Simple Deadlock Avoidance Scheme for Modular Systems-on-Chip
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ShuttleNoC: Power-Adaptable Communication Infrastructure for Many-Core Processors
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Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems
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SWAP: A Server-Scale Communication-Aware Chiplet-Based Manycore PIM Accelerator
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INDM: Chiplet-Based Interconnect Network and Dataflow Mapping for DNN Accelerators
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A Dataflow-Aware Network-on-Interposer for CNN Inferencing in the Presence of Defective Chiplets
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HeMu: Energy-Efficient DNN Inferencing via Heterogeneous Multichiplet Architectures
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Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems
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An Asymmetric, One-To-Many Traffic-Aware mm-Wave Wireless Interconnection Architecture for Multichip Systems
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HS-GCN: A High-Performance, Sustainable, and Scalable Chiplet-Based Accelerator for Graph Convolutional Network Inference
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Reconfigurable Fault-Tolerant Link With Bandwidth Expansion for 2.5-D Chiplet-Based Systems
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NERT: Network- and Routing-aware Testing of Interconnects in Fanout Wafer-Level Packaging.
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Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems
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Enabling interposer-based disintegration of multi-core processors
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Photonic Interconnects for Interposer-based 2.5D/3D Integrated Systems on a Chip
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Estimating and understanding architectural risk
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3D NoCs with active interposer for multi-die systems
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Enabling scalable chiplet-based uniform memory architectures with silicon photonics
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Reinforcement Learning Enabled Throughput Optimization for Interconnection Networks of Interposer-based system
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Flumen: Dynamic Processing in the Photonic Interconnect
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Coherence Attacks and Countermeasures in Interposer-based Chiplet Systems
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An Analysis of Various Design Pathways Towards Multi-Terabit Photonic On-Interposer Interconnects
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NetSmith: An Optimization Framework for Machine-Discovered Network Topologies
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AdCoalescer: An Adaptive Coalescer to Reduce the Inter-Module Traffic in MCM-GPUs
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PD Constraint-aware Physical/Logical Topology Co-Design for Network on Wafer
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SuperMesh: Energy-Efficient Collective Communications for Accelerators
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Design of Interposer Interconnection Network Based on High-Radix Interposer Routers
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Enabling Scalable Disintegrated Computing Systems With AWGR-Based 25D Interconnection Networks
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Adaptive Lossy Data Compression Extended Architecture for Memory Bandwidth Conservation in SpMV
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FTHOE: A Hamiltonian-Driven Fault-Tolerant Routing Algorithm for Wafer-Scale Interconnection Networks
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Improving the global memory efficiency in GPU-based systems
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On-Chip Networks, Second Edition
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Achieving Datacenter-scale Performance through Chiplet-based Manycore Architectures
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A Performance Analysis of Chiplet-Based Systems
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A Reusable Methodology for High-Performance Interconnects using a Standard-Cell based Asynchronous NoC Router
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The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems
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Remote Control: A Simple Deadlock Avoidance Scheme for Modular System on Chip
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Towards energy-efficient high-throughput photonic NoCs for 2.5D integrated systems: a case for AWGRs
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Novel approach for serial data link in 28nm CMOS FDSOI and beyond
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