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CoLT: Coalesced Large-Reach TLBs
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/hpca.2001.903252openalex-snapshot
Reevaluating online superpage promotion with hardware support
inferredcites →https://doi.org/10.1109/hpca.2011.5749717openalex-snapshot
Shared last-level TLBs for chip multiprocessors
inferredcites →https://doi.org/10.1109/isca.2002.1003578openalex-snapshot
Going the distance for TLB prefetching: an application-driven study
inferredcites →https://doi.org/10.1109/isca.2012.6237026openalex-snapshot
Reducing memory reference energy with opportunistic virtual caching
inferredcites →https://doi.org/10.1109/ispass.2005.1430554openalex-snapshot
BioBench: A Benchmark Suite of Bioinformatics Applications
inferredcites →https://doi.org/10.1109/ispass.2008.4510742openalex-snapshot
Investigating the TLB Behavior of High-end Scientific Applications on Commodity Microprocessors
inferredcites →https://doi.org/10.1109/pact.2009.26openalex-snapshot
Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors
inferredcites →https://doi.org/10.1145/1060289.1060299openalex-snapshot
Practical, transparent operating system support for superpages
inferredcites →https://doi.org/10.1145/1346281.1346286openalex-snapshot
Accelerating two-dimensional page walks for virtualized systems
inferredcites →https://doi.org/10.1145/139669.139708openalex-snapshot
A simulation based study of TLB performance
inferredcites →https://doi.org/10.1145/139669.140406openalex-snapshot
Tradeoffs in supporting two page sizes
inferredcites →https://doi.org/10.1145/165123.165127openalex-snapshot
Design tradeoffs for software-managed TLBs
inferredcites →https://doi.org/10.1145/195470.195531openalex-snapshot
Surpassing the TLB performance of superpages with less operating system support
inferredcites →https://doi.org/10.1145/195473.195531openalex-snapshot
Surpassing the TLB performance of superpages with less operating system support
inferredcites →https://doi.org/10.1145/214451.214455openalex-snapshot
Performance of the VAX-11/780 translation buffer
inferredcites →https://doi.org/10.1145/223982.224419openalex-snapshot
Reducing TLB and memory overhead using online superpage promotion
inferredcites →https://doi.org/10.1145/224056.224078openalex-snapshot
The impact of architectural trends on operating system performance
inferredcites →https://doi.org/10.1145/225830.224419openalex-snapshot
Reducing TLB and memory overhead using online superpage promotion
inferredcites →https://doi.org/10.1145/2366231.2337194openalex-snapshot
Reducing memory reference energy with opportunistic virtual caching
inferredcites →https://doi.org/10.1145/545214.545237openalex-snapshot
Going the distance for TLB prefetching
inferredcites →https://doi.org/10.1145/781027.781076openalex-snapshot
Using SimPoint for accurate and efficient simulation
inferredcites →https://doi.org/10.1145/844128.844138openalex-snapshot
Practical, transparent operating system support for superpages
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cpe.4061openalex-snapshot
A survey of techniques for architecting TLBs
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CoPTA: Contiguous Pattern Speculating TLB Architecture
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Superpage-Friendly Page Table Design for Hybrid Memory Systems
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Memory management technology based on homegrown multicore processor
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ACOPT: Adaptive continuity-aware address translation for performance optimization of MCM-GPU architectures
inferred← citeshttps://doi.org/10.1109/access.2020.2983065openalex-snapshot
TLB Coalescing for Multi-Grained Page Migration in Hybrid Memory Systems
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Page Table Compaction for TLB Coalescing
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CFFS: A Persistent Memory File System for Contiguous File Allocation With Fine-Grained Metadata
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Page-Size Aware Buddy Allocator With Unaligned Range Supports for TLB Coalescing
inferred← citeshttps://doi.org/10.1109/access.2025.3528945openalex-snapshot
TLB Coalescing With Range Compressed Page Table for Embedded I/O Devices
inferred← citeshttps://doi.org/10.1109/access.2026.3658672openalex-snapshot
Clustered Page Table Compression for TLB Coalescing
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Orchestrated Scheduling and Partitioning for Improved Address Translation in GPUs
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Classification-Based Unified Cache Replacement via Partitioned Victim Address History
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PT-Guard: Integrity-Protected Page Tables to Defend Against Breakthrough Rowhammer Attacks
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835964openalex-snapshot
Increasing TLB reach by exploiting clustering in page translations
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056034openalex-snapshot
Prediction-based superpage-friendly TLB designs
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056035openalex-snapshot
Supporting superpages in non-contiguous physical memory
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446100openalex-snapshot
Energy-efficient address translation
inferred← citeshttps://doi.org/10.1109/hpca.2018.00020openalex-snapshot
SIPT: Speculatively Indexed, Physically Tagged Caches
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00050openalex-snapshot
Dead Page and Dead Block Predictors: Cleaning TLBs and Caches Together
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00059openalex-snapshot
Improving GPU Multi-tenancy with Page Walk Stealing
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071054openalex-snapshot
Trans-FW: Short Circuiting Page Table Walk in Multi-GPU Systems via Remote Forwarding
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Memory-Efficient Hashed Page Tables
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071063openalex-snapshot
SnakeByte: A TLB Design with Adaptive and Recursive Page Merging in GPUs
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Marching Page Walks: Batching and Concurrent Page Table Walks for Enhancing GPU Throughput
inferred← citeshttps://doi.org/10.1109/hpcc67675.2025.00076openalex-snapshot
LAMP: A Locality-Aware TLB Sharing Framework for Multi-Tenant GPUs via TLB Comprehensive Profiling
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HeronEye: Survey on Coordinated and Efficient Huge Page Management to Fine-grained OS Support
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Scattered superpage: A case for bridging the gap between superpage and page coloring
inferred← citeshttps://doi.org/10.1109/iccd.2014.6974692openalex-snapshot
BarTLB: Barren page resistant TLB for managed runtime languages
inferred← citeshttps://doi.org/10.1109/iccd50377.2020.00052openalex-snapshot
Unified-TP: A Unified TLB and Page Table Cache Structure for Efficient Address Translation
inferred← citeshttps://doi.org/10.1109/iiswc.2014.6983034openalex-snapshot
Performance analysis of the memory management unit under scale-out workloads
inferred← citeshttps://doi.org/10.1109/iiswc55918.2022.00026openalex-snapshot
The Implications of Page Size Management on Graph Analytics
inferred← citeshttps://doi.org/10.1109/isca.2016.18openalex-snapshot
Efficient Synonym Filtering and Scalable Delayed Translation for Hybrid Virtual Caching
inferred← citeshttps://doi.org/10.1109/isca.2016.28openalex-snapshot
Efficient synonym filtering and scalable delayed translation for hybrid virtual caching
inferred← citeshttps://doi.org/10.1109/isca.2016.67openalex-snapshot
Agile Paging: Exceeding the Best of Nested and Shadow Paging
inferred← citeshttps://doi.org/10.1109/isca.2018.00025openalex-snapshot
Scheduling Page Table Walks for Irregular GPU Applications
inferred← citeshttps://doi.org/10.1109/isca.2018.00026openalex-snapshot
SEESAW: Using Superpages to Improve VIPT Caches
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00049openalex-snapshot
BabelFish: Fusing Address Translations for Containers
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00050openalex-snapshot
Enhancing and Exploiting Contiguity for Fast Memory Virtualization
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00079openalex-snapshot
Perforated Page: Supporting Fragmented Memory Allocation for Large Pages
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00089openalex-snapshot
The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00016openalex-snapshot
Exploiting Page Table Locality for Agile TLB Prefetching
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00047openalex-snapshot
Rebooting Virtual Memory with Midgard
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00065openalex-snapshot
Barre Chord: Efficient Virtual Memory Translation for Multi-Chip-Module GPUs
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00085openalex-snapshot
DyLeCT: Achieving Huge-page-like Translation Performance for Hardware-compressed Memory
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Reducing Page Faults via Invalidation-Based Mapping Propagation in Multi-GPU Systems
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BulletTime: Time Dilation for High-Fidelity Tracing
inferred← citeshttps://doi.org/10.1109/ispa-bdcloud-socialcom-sustaincom51426.2020.00038openalex-snapshot
A Unified Page Walk Buffer and Page Walk Cache
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Observations and opportunities in architecting shared virtual memory for heterogeneous systems
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On the Impact of Instruction Address Translation Overhead
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TLB Shootdown Mitigation for Low-Power Many-Core Servers with L1 Virtual Caches
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Towards Segmentation-Based Address Translation for LLM Inference
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Prospects for Functional Address Translation
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Representing Contiguity in Page Table for Memory Management Units
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Efficient Memory Virtualization: Reducing Dimensionality of Nested Page Walks
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Scalable Distributed Last-Level TLBs Using Low-Latency Interconnects
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Neighborhood-Aware Address Translation for Irregular GPU Applications
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CHiRP: Control-Flow History Reuse Prediction
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Elastic Translations: Fast Virtual Memory with Multiple Translation Sizes
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A Case for Speculative Address Translation with Rapid Validation for GPUs
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STAR: Sub-Entry Sharing-Aware TLB for Multi-Instance GPU
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Address Translation for Throughput-Oriented Accelerators
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Preserving Virtual Memory by Mitigating the Address Translation Wall
inferred← citeshttps://doi.org/10.1109/mm.2018.032271063openalex-snapshot
Breaking the Address Translation Wall by Accelerating Memory Replays
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Contiguitas: The Pursuit of Physical Memory Contiguity in Data Centers
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HugeGPT: Storing Guest Page Tables on Host Huge Pages to Accelerate Address Translation
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SecureCells: A Secure Compartmentalized Architecture
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Fast Two-Level Address Translation for Virtualized Systems
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Disaggregated Cloud Memory with Elastic Block Management
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GCMA: Guaranteed Contiguous Memory Allocator
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HashScape: Leveraging Virtual Address Dynamics for Efficient Hashed Page Tables
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Contiguity Representation in Page Table for Memory Management Units
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CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration
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DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems
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Efficient virtual memory for big memory servers
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Efficient virtual memory for big memory servers
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Large-reach memory management unit caches
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Architectural support for address translation on GPUs
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Revisiting virtual memory for high performance computing on manycore architectures
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Architectural support for address translation on GPUs
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Architectural support for address translation on GPUs
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Redundant memory mappings for fast access to large memories
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Large pages and lightweight memory management in virtualized environments
inferred← citeshttps://doi.org/10.1145/2830772.2830792openalex-snapshot
Microarchitectural implications of event-driven server-side web applications
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Redundant memory mappings for fast access to large memories
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Efficient synonym filtering and scalable delayed translation for hybrid virtual caching
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Efficient synonym filtering and scalable delayed translation for hybrid virtual caching
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Efficient Address Translation for Architectures with Multiple Page Sizes
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Translation-Triggered Prefetching
inferred← citeshttps://doi.org/10.1145/3079856.3080210openalex-snapshot
Rethinking TLB Designs in Virtualized Environments
inferred← citeshttps://doi.org/10.1145/3079856.3080211openalex-snapshot
Hardware Translation Coherence for Virtualized Systems
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Efficient Address Translation for Architectures with Multiple Page Sizes
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Translation-Triggered Prefetching
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Hardware Translation Coherence for Virtualized Systems
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Devirtualizing Memory in Heterogeneous Systems
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Filtering Translation Bandwidth with Virtual Caching
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Secure, Consistent, and High-Performance Memory Snapshotting
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Revisiting Multi-pass Scatter and Gather on GPUs
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Hardware Translation Coherence for Virtualized Systems
inferred← citeshttps://doi.org/10.1145/3296957.3173194openalex-snapshot
Devirtualizing Memory in Heterogeneous Systems
inferred← citeshttps://doi.org/10.1145/3296957.3173195openalex-snapshot
Filtering Translation Bandwidth with Virtual Caching
inferred← citeshttps://doi.org/10.1145/3297858.3304044openalex-snapshot
A Framework for Memory Oversubscription Management in Graphics Processing Units
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Supporting Superpages and Lightweight Page Migration in Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1145/3352460.3358294openalex-snapshot
Prefetched Address Translation
inferred← citeshttps://doi.org/10.1145/3369583.3392670openalex-snapshot
PAC: Paged Adaptive Coalescer for 3D-Stacked Memory
inferred← citeshttps://doi.org/10.1145/3373376.3378468openalex-snapshot
Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory Machines
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Paging and the Address-Translation Problem
inferred← citeshttps://doi.org/10.1145/3410463.3414633openalex-snapshot
Enhancing Address Translations in Throughput Processors via Compression
inferred← citeshttps://doi.org/10.1145/3422575.3422804openalex-snapshot
PreFAM: Understanding the Impact of Prefetching in Fabric-Attached Memory Architectures
inferred← citeshttps://doi.org/10.1145/3433210.3453077openalex-snapshot
(Mis)managed: A Novel TLB-based Covert Channel on GPUs
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PTEMagnet: fine-grained physical memory reservation for faster page walks in public clouds
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Fast local page-tables for virtualized NUMA servers with vMitosis
inferred← citeshttps://doi.org/10.1145/3466752.3480049openalex-snapshot
Morrigan: A Composite Instruction TLB Prefetcher
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Trident: Harnessing Architectural Resources for All Page Sizes in x86 Processors
inferred← citeshttps://doi.org/10.1145/3466752.3480083openalex-snapshot
Improving Address Translation in Multi-GPUs via Sharing and Spilling aware TLB Design
inferred← citeshttps://doi.org/10.1145/3503222.3507718openalex-snapshot
Every walk’s a hit: making page walks single-access cache hits
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Parallel virtualized memory translation with nested elastic cuckoo page tables
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T unne L s for B ootlegging: Fully Reverse-Engineering GPU TLBs for Challenging Isolation Guarantees of NVIDIA MIG
inferred← citeshttps://doi.org/10.1145/3579371.3589079openalex-snapshot
Contiguitas: The Pursuit of Physical Memory Contiguity in Datacenters
inferred← citeshttps://doi.org/10.1145/3579371.3589080openalex-snapshot
Spy in the GPU-box: Covert and Side Channel Attacks on Multi-GPU Systems
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Mosaic Pages: Big TLB Reach with Small Pages
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Reconfigurable Virtual Memory for FPGA-Driven I/O
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The Impact of Page Size and Microarchitecture on Instruction Address Translation Overhead
inferred← citeshttps://doi.org/10.1145/3613424.3614269openalex-snapshot
IDYLL: Enhancing Page Translation in Multi-GPUs via Light Weight PTE Invalidations
inferred← citeshttps://doi.org/10.1145/3613424.3614276openalex-snapshot
Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources
inferred← citeshttps://doi.org/10.1145/3613424.3614293openalex-snapshot
Accelerating Extra Dimensional Page Walks for Confidential Computing
inferred← citeshttps://doi.org/10.1145/3613424.3614296openalex-snapshot
Architectural Support for Optimizing Huge Page Selection Within the OS
inferred← citeshttps://doi.org/10.1145/3620665.3640358openalex-snapshot
Direct Memory Translation for Virtualized Clouds
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WASP: Workload-Aware Self-Replicating Page-Tables for NUMA Servers
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An Empirical Evaluation of PTE Coalescing
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Rethinking Page Table Structure for Fast Address Translation in GPUs: A Fixed-Size Hashed Page Table
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Virtuoso: Enabling Fast and Accurate Virtual Memory Research via an Imitation-based Operating System Simulation Methodology
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Heliostat: Harnessing Ray Tracing Accelerators for Page Table Walks
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Garibaldi: A Pairwise Instruction-Data Management for Enhancing Shared Last-Level Cache Performance in Server Workloads
inferred← citeshttps://doi.org/10.1145/3725843.3756056openalex-snapshot
SoftWalker: Supporting Software Page Table Walk for Irregular GPU Applications
inferred← citeshttps://doi.org/10.1145/3725843.3756069openalex-snapshot
LATPC: Accelerating GPU Address Translation Using Locality-Aware TLB Prefetching and MSHR Compression
inferred← citeshttps://doi.org/10.1145/3725843.3756090openalex-snapshot
Leveraging Chiplet-Locality for Efficient Memory Mapping in Multi-Chip Module GPUs
inferred← citeshttps://doi.org/10.1145/3725843.3756093openalex-snapshot
Learning to Walk: Architecting Learned Virtual Memory Translation
inferred← citeshttps://doi.org/10.1145/3735950.3735952openalex-snapshot
EMD: Fair and Efficient Dynamic Memory De-bloating of Transparent Huge Pages
inferred← citeshttps://doi.org/10.1145/3801487.3801813openalex-snapshot
NoCWalk: In-Network Page Walks for Efficient Pointer-Chasing Workloads on Multicores
inferred← citeshttps://doi.org/10.1145/3802921openalex-snapshot
Making Hardware Features Bespoke: Operating System Support for Bes-Mode Processes
inferred← citeshttps://doi.org/10.1145/3805633openalex-snapshot
cuPTW: Leveraging Idle Compute Units for Massively Parallel GPU Page Table Walks
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Techniques for Shared Resource Management in Systems with Throughput Processors
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Contiguity aware TLB prefetching for embedded I/O devices
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Page table level aware buddy system for TLB coalescing
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Virtual Address Remapping with Configurable Tiles in Image Processing Applications
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Architectural and Operating System Support for Virtual Memory
inferred← citeshttps://doi.org/10.23919/date54114.2022.9774723openalex-snapshot
GATLB: A Granularity-Aware TLB to Support Multi-Granularity Pages in Hybrid Memory System
inferred← citeshttps://doi.org/10.23919/date64628.2025.10992962openalex-snapshot
Evaluating IOMMU-Based Shared Virtual Addressing for RISC-V Embedded Heterogeneous SoCs
inferred← citeshttps://doi.org/10.3390/electronics14081685openalex-snapshot
Latency-Aware and Auto-Migrating Page Tables for ARM NUMA Servers
inferred← citeshttps://doi.org/10.48550/arxiv.1612.00445openalex-snapshot
Near-Memory Address Translation
inferred← citeshttps://doi.org/10.48550/arxiv.1701.03499openalex-snapshot
VESPA: VIPT Enhancements for Superpage Accesses
inferred← citeshttps://doi.org/10.48550/arxiv.1707.09450openalex-snapshot
Address Translation Design Tradeoffs for Heterogeneous Systems
inferred← citeshttps://doi.org/10.48550/arxiv.1905.06825openalex-snapshot
Fast TLB Simulation for RISC-V Systems
inferred← citeshttps://doi.org/10.48550/arxiv.1906.10347openalex-snapshot
ALTIS: Modernizing GPGPU Benchmarking
inferred← citeshttps://doi.org/10.48550/arxiv.1908.08774openalex-snapshot
Coalesced TLB to Exploit Diverse Contiguity of Memory Mapping
inferred← citeshttps://doi.org/10.48550/arxiv.2001.07045openalex-snapshot
SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators
inferred← citeshttps://doi.org/10.48550/arxiv.2002.01073openalex-snapshot
TLB and Pagewalk Performance in Multicore Architectures with Large Die-Stacked DRAM Cache
inferred← citeshttps://doi.org/10.48550/arxiv.2009.07723openalex-snapshot
Enabling Virtual Memory Research on RISC-V with a Configurable TLB Hierarchy for the Rocket Chip Generator
inferred← citeshttps://doi.org/10.48550/arxiv.2011.12092openalex-snapshot
Leveraging Architectural Support of Three Page Sizes with Trident
inferred← citeshttps://doi.org/10.48550/arxiv.2012.05079openalex-snapshot
Page Tables: Keeping them Flat and Hot (Cached)
inferred← citeshttps://doi.org/10.48550/arxiv.2110.08613openalex-snapshot
Enabling Large-Reach TLBs for High-Throughput Processors by Exploiting Memory Subregion Contiguity
inferred← citeshttps://doi.org/10.4995/thesis/10251/86136openalex-snapshot
Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors
inferred← citeshttps://doi.org/10.4995/thesis/10251/86187openalex-snapshot
Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors
inferred← citeshttps://doi.org/10.5555/3026877.3026931openalex-snapshot
Coordinated and efficient huge page management with ingens
inferred← citeshttps://doi.org/10.5821/dissertation-2117-403959openalex-snapshot
Advanced hardware prefetching in virtual memory systems
inferred← citeshttps://doi.org/10.5821/dissertation-2117-96333openalex-snapshot
Improving the performance and energy-efficiency of virtual memory
inferred← citeshttps://doi.org/10.7282/t3-m0cq-tt95openalex-snapshot
Improving and complementing virtual memory using hardware techniques
inferred← citeshttps://doi.org/10.7282/t3qc073nopenalex-snapshot
Using TLB Speculation to Overcome Page Splintering in Virtual Machines
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