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DUCATI

https://doi.org/10.1145/3309710
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1016/b978-0-12-809194-4.00002-8openalex-snapshot
Knights Landing overview
inferredcites →https://doi.org/10.1109/12.2242openalex-snapshot
Machine-independent virtual memory management for paged uniprocessor and multiprocessor architectures
inferredcites →https://doi.org/10.1109/2.683005openalex-snapshot
Virtual memory: issues of implementation
inferredcites →https://doi.org/10.1109/hotchips.2015.7477461openalex-snapshot
AMD's next generation GPU and high bandwidth memory architecture: FURY
inferredcites →https://doi.org/10.1109/hpca.2011.5749717openalex-snapshot
Shared last-level TLBs for chip multiprocessors
inferredcites →https://doi.org/10.1109/hpca.2012.6168947openalex-snapshot
TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture
inferredcites →https://doi.org/10.1109/hpca.2014.6835964openalex-snapshot
Increasing TLB reach by exploiting clustering in page translations
inferredcites →https://doi.org/10.1109/hpca.2014.6835965openalex-snapshot
Supporting x86-64 address translation for 100s of GPU lanes
inferredcites →https://doi.org/10.1109/hpca.2016.7446077openalex-snapshot
Towards high performance paged memory for GPUs
inferredcites →https://doi.org/10.1109/hpcsim.2012.6266938openalex-snapshot
The Intel® Many Integrated Core Architecture
inferredcites →https://doi.org/10.1109/isca.2018.00036openalex-snapshot
ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-Prediction
inferredcites →https://doi.org/10.1109/ispass.2009.4919639openalex-snapshot
Lonestar: A suite of parallel irregular programs
inferredcites →https://doi.org/10.1109/ispass.2016.7482091openalex-snapshot
Observations and opportunities in architecting shared virtual memory for heterogeneous systems
inferredcites →https://doi.org/10.1109/micro.2012.30openalex-snapshot
Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design
inferredcites →https://doi.org/10.1109/micro.2012.31openalex-snapshot
A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch
inferredcites →https://doi.org/10.1109/micro.2012.32openalex-snapshot
CoLT: Coalesced Large-Reach TLBs
inferredcites →https://doi.org/10.1109/micro.2014.51openalex-snapshot
Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache
inferredcites →https://doi.org/10.1109/micro.2014.63openalex-snapshot
CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache
inferredcites →https://doi.org/10.1109/micro.2018.00035openalex-snapshot
Combining HW/SW Mechanisms to Improve NUMA Performance of Multi-GPU Systems
inferredcites →https://doi.org/10.1109/mm.2013.49openalex-snapshot
The Oracle Sparc T5 16-Core Processor Scales to Eight Sockets
inferredcites →https://doi.org/10.1109/mm.2016.25openalex-snapshot
Knights Landing: Second-Generation Intel Xeon Phi Product
inferredcites →https://doi.org/10.1145/1188455.1188677openalex-snapshot
S12---The HPC Challenge (HPCC) benchmark suite
inferredcites →https://doi.org/10.1145/1250662.1250709openalex-snapshot
Adaptive insertion policies for high performance caching
inferredcites →https://doi.org/10.1145/1346281.1346286openalex-snapshot
Accelerating two-dimensional page walks for virtualized systems
inferredcites →https://doi.org/10.1145/139669.139708openalex-snapshot
A simulation based study of TLB performance
inferredcites →https://doi.org/10.1145/139669.140406openalex-snapshot
Tradeoffs in supporting two page sizes
inferredcites →https://doi.org/10.1145/17356.17398openalex-snapshot
An in-cache address translation mechanism
inferredcites →https://doi.org/10.1145/1736020.1736060openalex-snapshot
Inter-core cooperative TLB for chip multiprocessors
inferredcites →https://doi.org/10.1145/1815961.1815970openalex-snapshot
Translation caching
inferredcites →https://doi.org/10.1145/1815961.1815971openalex-snapshot
High performance cache replacement using re-reference interval prediction (RRIP)
inferredcites →https://doi.org/10.1145/1854273.1854333openalex-snapshot
Using dead blocks as a virtual victim cache
inferredcites →https://doi.org/10.1145/195470.195531openalex-snapshot
Surpassing the TLB performance of superpages with less operating system support
inferredcites →https://doi.org/10.1145/195473.195531openalex-snapshot
Surpassing the TLB performance of superpages with less operating system support
inferredcites →https://doi.org/10.1145/2000064.2000101openalex-snapshot
SpecTLB
inferredcites →https://doi.org/10.1145/2024723.2000101openalex-snapshot
SpecTLB
inferredcites →https://doi.org/10.1145/2155620.2155624openalex-snapshot
Minimalist open-page
inferredcites →https://doi.org/10.1145/2155620.2155671openalex-snapshot
SHiP
inferredcites →https://doi.org/10.1145/2155620.2155673openalex-snapshot
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
inferredcites →https://doi.org/10.1145/234313.234403openalex-snapshot
Virtual memory
inferredcites →https://doi.org/10.1145/237090.237205openalex-snapshot
Operating system support for improving data locality on CC-NUMA compute servers
inferredcites →https://doi.org/10.1145/2451116.2451157openalex-snapshot
Traffic management
inferredcites →https://doi.org/10.1145/2485922.2485943openalex-snapshot
Efficient virtual memory for big memory servers
inferredcites →https://doi.org/10.1145/2485922.2485958openalex-snapshot
Resilient die-stacked DRAM caches
inferredcites →https://doi.org/10.1145/2540708.2540733openalex-snapshot
Insertion and promotion for tree-based PseudoLRU last-level caches
inferredcites →https://doi.org/10.1145/2540708.2540741openalex-snapshot
Large-reach memory management unit caches
inferredcites →https://doi.org/10.1145/2541940.2541942openalex-snapshot
Architectural support for address translation on GPUs
inferredcites →https://doi.org/10.1145/2694344.2694381openalex-snapshot
Page Placement Strategies for GPUs within Heterogeneous Memory Systems
inferredcites →https://doi.org/10.1145/2749469.2750387openalex-snapshot
BEAR
inferredcites →https://doi.org/10.1145/2830772.2830773openalex-snapshot
Large pages and lightweight memory management in virtualized environments
inferredcites →https://doi.org/10.1145/30350openalex-snapshot
Proceedings of the 14th annual international symposium on Computer architecture - ISCA '87
inferredcites →https://doi.org/10.1145/3079856.3080210openalex-snapshot
Rethinking TLB Designs in Virtualized Environments
inferredcites →https://doi.org/10.1145/339647.339666openalex-snapshot
Recency-based TLB preloading
inferredcites →https://doi.org/10.1145/545214.545237openalex-snapshot
Going the distance for TLB prefetching
inferredcites →https://doi.org/10.1145/74850.74854openalex-snapshot
Simple but effective techniques for NUMA memory management
inferredcites →https://doi.org/10.2172/993908openalex-snapshot
Improving performance via mini-applications.

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00055openalex-snapshot
Griffin: Hardware-Software Support for Efficient Page Migration in Multi-GPU Systems
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071054openalex-snapshot
Trans-FW: Short Circuiting Page Table Walk in Multi-GPU Systems via Remote Forwarding
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071063openalex-snapshot
SnakeByte: A TLB Design with Adaptive and Recursive Page Merging in GPUs
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00088openalex-snapshot
GPU Scale-Model Simulation
inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00123openalex-snapshot
Marching Page Walks: Batching and Concurrent Page Table Walks for Enhancing GPU Throughput
inferred← citeshttps://doi.org/10.1109/iccd56317.2022.00031openalex-snapshot
Enhancing GPU Performance via Neighboring Directory Table Based Inter-TLB Sharing
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00065openalex-snapshot
Barre Chord: Efficient Virtual Memory Translation for Multi-Chip-Module GPUs
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00110openalex-snapshot
Reducing Page Faults via Invalidation-Based Mapping Propagation in Multi-GPU Systems
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00029openalex-snapshot
A Case for Speculative Address Translation with Rapid Validation for GPUs
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00030openalex-snapshot
SUV: Static Analysis Guided Unified Virtual Memory
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00051openalex-snapshot
Low-Overhead General-Purpose Near-Data Processing in CXL Memory Expanders
inferred← citeshttps://doi.org/10.1142/s0218126621502923openalex-snapshot
LPE: Locality-Based Dead Prediction in Exclusive TLB for Large Coverage
inferred← citeshttps://doi.org/10.1145/3410463.3414639openalex-snapshot
Valkyrie
inferred← citeshttps://doi.org/10.1145/3466752.3480083openalex-snapshot
Improving Address Translation in Multi-GPUs via Sharing and Spilling aware TLB Design
inferred← citeshttps://doi.org/10.1145/3466752.3480100openalex-snapshot
Principal Kernel Analysis: A Tractable Methodology to Simulate Scaled GPU Workloads
inferred← citeshttps://doi.org/10.1145/3466752.3480105openalex-snapshot
Increasing GPU Translation Reach by Leveraging Under-Utilized On-Chip Resources
inferred← citeshttps://doi.org/10.1145/3508352.3549431openalex-snapshot
Qilin
inferred← citeshttps://doi.org/10.1145/3514221.3517911openalex-snapshot
Triton Join: Efficiently Scaling to a Large Join State on GPUs with Fast Interconnects
inferred← citeshttps://doi.org/10.1145/3605573.3605593openalex-snapshot
GPU Performance Acceleration via Intra-Group Sharing TLB
inferred← citeshttps://doi.org/10.1145/3620665.3640358openalex-snapshot
Direct Memory Translation for Virtualized Clouds
inferred← citeshttps://doi.org/10.1145/3656019.3676900openalex-snapshot
Rethinking Page Table Structure for Fast Address Translation in GPUs: A Fixed-Size Hashed Page Table
inferred← citeshttps://doi.org/10.1145/3694715.3695957openalex-snapshot
VPRI: Efficient I/O Page Fault Handling via Software-Hardware Co-Design for IaaS Clouds
inferred← citeshttps://doi.org/10.1145/3695053.3731011openalex-snapshot
Heliostat: Harnessing Ray Tracing Accelerators for Page Table Walks
inferred← citeshttps://doi.org/10.1145/3725843.3756069openalex-snapshot
LATPC: Accelerating GPU Address Translation Using Locality-Aware TLB Prefetching and MSHR Compression
inferred← citeshttps://doi.org/10.1145/3725843.3756090openalex-snapshot
Leveraging Chiplet-Locality for Efficient Memory Mapping in Multi-Chip Module GPUs
inferred← citeshttps://doi.org/10.1145/3725843.3756093openalex-snapshot
Learning to Walk: Architecting Learned Virtual Memory Translation
inferred← citeshttps://doi.org/10.1145/3805633openalex-snapshot
cuPTW: Leveraging Idle Compute Units for Massively Parallel GPU Page Table Walks
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