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Machine Learning Enabled Solutions for Design and Optimization Challenges in Networks-on-Chip based Multi/Many-Core Architectures
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4614-8274-1openalex-snapshot
Routing Algorithms in Networks-on-Chip
inferredcites →https://doi.org/10.1007/s10825-004-7038-9openalex-snapshot
A Computational Model of NBTI and Hot Carrier Injection Time-Exponents for MOSFET Reliability
inferredcites →https://doi.org/10.1007/s11227-011-0703-4openalex-snapshot
Toward on-chip datacenters: a perspective on general trends and on-chip particulars
inferredcites →https://doi.org/10.1007/s11227-014-1144-7openalex-snapshot
A task migration mechanism for distributed many-core operating systems
inferredcites →https://doi.org/10.1016/j.compeleceng.2013.08.006openalex-snapshot
A hybrid packet-circuit switched router for optical network on chip
inferredcites →https://doi.org/10.1016/j.compeleceng.2018.04.019openalex-snapshot
Hotspot-aware task-resource co-allocation for heterogeneous many-core networks-on-chip
inferredcites →https://doi.org/10.1049/ip-cdt:20045100openalex-snapshot
Network-on-chip architectures and design methods
inferredcites →https://doi.org/10.1109/40.782564openalex-snapshot
Design challenges of technology scaling
inferredcites →https://doi.org/10.1109/71.219761openalex-snapshot
Deadlock-free adaptive routing in multicomputer networks using virtual channels
inferredcites →https://doi.org/10.1109/access.2022.3182500openalex-snapshot
Deep Reinforcement Learning Enabled Self-Configurable Networks-on-Chip for High-Performance and Energy-Efficient Computing Systems
inferredcites →https://doi.org/10.1109/aspdac.2012.6165027openalex-snapshot
A learning-based autoregressive model for fast transient thermal analysis of chip-multiprocessors
inferredcites →https://doi.org/10.1109/dac.1997openalex-snapshot
Proceedings of the 34th Design Automation Conference
inferredcites →https://doi.org/10.1109/dac18074.2021.9586301openalex-snapshot
Distilling Arbitration Logic from Traces using Machine Learning: A Case Study on NoC
inferredcites →https://doi.org/10.1109/dsn.2004.1311857openalex-snapshot
2004 International Conference on Dependable Systems and Networks
inferredcites →https://doi.org/10.1109/hpca.2010.5416640openalex-snapshot
Simple virtual channel allocation for high throughput and high frequency on-chip routers
inferredcites →https://doi.org/10.1109/iccad.2015.7372639openalex-snapshot
Optimizing 3D NoC design for energy efficiency: A machine learning approach
inferredcites →https://doi.org/10.1109/iccad45719.2019.8942108openalex-snapshot
Proceedings of the 2019 International Conference on Computer-Aided Design (ICCAD)
inferredcites →https://doi.org/10.1109/isca.2005.34openalex-snapshot
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
inferredcites →https://doi.org/10.1109/isscc.2014.6757323openalex-snapshot
1.1 Computing's energy problem (and what we can do about it)
inferredcites →https://doi.org/10.1109/isvlsi.2014.36openalex-snapshot
A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-Based MPSoCs
inferredcites →https://doi.org/10.1109/jssc.1974.1050511openalex-snapshot
Design of ion-implanted MOSFET's with very small physical dimensions
inferredcites →https://doi.org/10.1109/jssc.2016.2638459openalex-snapshot
KiloCore: A 32-nm 1000-Processor Computational Array
inferredcites →https://doi.org/10.1109/mc.2005.379openalex-snapshot
Heterogeneous chip multiprocessors
inferredcites →https://doi.org/10.1109/mc.2018.3011040openalex-snapshot
Machine Learning and Manycore Systems Design: A Serendipitous Symbiosis
inferredcites →https://doi.org/10.1109/micro.2008.4771806openalex-snapshot
Power reduction of CMP communication networks via RF-interconnects
inferredcites →https://doi.org/10.1109/micro.2012.33openalex-snapshot
NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers
inferredcites →https://doi.org/10.1109/micro.2016.7783734openalex-snapshot
Dynamic error mitigation in NoCs using intelligent prediction techniques
inferredcites →https://doi.org/10.1109/mm.2002.997877openalex-snapshot
The Raw microprocessor: a computational fabric for software circuits and general-purpose programs
inferredcites →https://doi.org/10.1109/mm.2005.110openalex-snapshot
Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation
inferredcites →https://doi.org/10.1109/mm.2007.4378783openalex-snapshot
A 5-GHz Mesh Interconnect for a Teraflops Processor
inferredcites →https://doi.org/10.1109/mm.2012.17openalex-snapshot
Dark Silicon and the End of Multicore Scaling
inferredcites →https://doi.org/10.1109/mm.2013.90openalex-snapshot
A Landscape of the New Dark Silicon Design Regime
inferredcites →https://doi.org/10.1109/nocs.2007.6openalex-snapshot
A Power and Energy Exploration of Network-on-Chip Architectures
inferredcites →https://doi.org/10.1109/nocs.2012.31openalex-snapshot
DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling
inferredcites →https://doi.org/10.1109/tc.2005.134openalex-snapshot
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
inferredcites →https://doi.org/10.1109/tc.2018.2875476openalex-snapshot
Dynamic Voltage and Frequency Scaling in NoCs with Supervised and Reinforcement Learning Techniques
inferredcites →https://doi.org/10.1109/tcad.2011.2160348openalex-snapshot
Memory-Efficient On-Chip Network With Adaptive Interfaces
inferredcites →https://doi.org/10.1109/tcad.2011.2170568openalex-snapshot
Intelligent Hotspot Prediction for Network-on-Chip-Based Multicore Systems
inferredcites →https://doi.org/10.1109/tvlsi.2006.878263openalex-snapshot
"It's a small world after all": NoC performance optimization via long-range link insertion
inferredcites →https://doi.org/10.1109/tvlsi.2007.893649openalex-snapshot
3-D Topologies for Networks-on-Chip
inferredcites →https://doi.org/10.1109/tvlsi.2019.2897650openalex-snapshot
Self-Optimizing and Self-Programming Computing Systems: A Combined Compiler, Complex Networks, and Machine Learning Approach
inferredcites →https://doi.org/10.1145/1278480.1278509openalex-snapshot
Voltage-frequency island partitioning for GALS-based networks-on-chip
inferredcites →https://doi.org/10.1145/1289816.1289857openalex-snapshot
Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels
inferredcites →https://doi.org/10.1145/146628.140384openalex-snapshot
The turn model for adaptive routing
inferredcites →https://doi.org/10.1145/1555815.1555781openalex-snapshot
A case for bufferless routing in on-chip networks
inferredcites →https://doi.org/10.1145/1645213.1645230openalex-snapshot
Hybrid wireless Network on Chip
inferredcites →https://doi.org/10.1145/1941487.1941507openalex-snapshot
The future of microprocessors
inferredcites →https://doi.org/10.1145/2967614openalex-snapshot
Electro-Photonic NoC Designs for Kilocore Systems
inferredcites →https://doi.org/10.1145/3055202openalex-snapshot
Efficient Mapping of Applications for Future Chip-Multiprocessors in Dark Silicon Era
inferredcites →https://doi.org/10.1145/3477231.3490427openalex-snapshot
Machine learning for design and optimization challenges in multi/many-core network-on-chip
inferredcites →https://doi.org/10.1155/2012/107821openalex-snapshot
Intelligent On/Off Dynamic Link Management for On‐Chip Networks
inferredcites →https://doi.org/10.1201/b10477openalex-snapshot
Designing Network On-Chip Architectures in the Nanoscale Era
inferredcites →https://doi.org/10.23919/date.2019.8714869openalex-snapshot
High-performance, energy-efficient, fault-tolerant network-on-chip design using reinforcement learning
inferredcites →https://doi.org/10.7873/date.2013.083openalex-snapshot
SVR-NoC: A Performance Analysis Tool for Network-on-Chips Using Learning-based Support Vector Regression Model
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/dac.6049openalex-snapshot
Improved Deep Reinforcement Learning With Faster Graph Recurrent Convolutional Neural Network‐Enabled Adaptive Network Slicing for Tailored Service Delivery in NextGen Networks
inferred← citeshttps://doi.org/10.1007/s00521-026-12049-4openalex-snapshot
NOCTOPUS: Network-on-Chip topology optimization and prediction using simulation-data
inferred← citeshttps://doi.org/10.1007/s11227-026-08443-3openalex-snapshot
Adaptive arbitration mechanisms for heterogeneous NoCs under diverse load scenarios
inferred← citeshttps://doi.org/10.1016/j.vlsi.2026.102831openalex-snapshot
A dynamic selection framework for network-on-chip routing algorithms based on deep reinforcement learning with temporal feature extraction
inferred← citeshttps://doi.org/10.1038/s41598-025-20381-3openalex-snapshot
Fault tolerant and quality of service aware routing algorithm based on priority technique for scalable network on chip architectures
inferred← citeshttps://doi.org/10.1038/s41598-025-96335-6openalex-snapshot
Reinforcement learning-driven task migration for effective temperature management in 3D noc systems
inferred← citeshttps://doi.org/10.1109/access.2023.3329233openalex-snapshot
A Survey on Dynamic Application Mapping Approaches for Real-Time Network-on-Chip-Based Platforms
inferred← citeshttps://doi.org/10.1109/gecost66002.2025.11324917openalex-snapshot
Load Balanced Congestion Aware Routing Algorithm for Wireless Network-on-Chip
inferred← citeshttps://doi.org/10.1109/icca66035.2025.11431020openalex-snapshot
Efficient Routing Scheme Using Quadrant Turn Model for 2D Mesh NoC Architecture
inferred← citeshttps://doi.org/10.1109/iicspi66775.2025.11438001openalex-snapshot
Research on Thermal Management Algorithm for Chips with Few-Shot Deep Reinforcement Learning Integrating Graph Neural Networks
inferred← citeshttps://doi.org/10.1109/mcsoc64144.2024.00065openalex-snapshot
Hierarchical Fault-Tolerant NoC Architecture for Reliable Communication
inferred← citeshttps://doi.org/10.1109/vlsitsa60681.2024.10546359openalex-snapshot
Application-Architecture Mapping for Energy-Efficiency and High-Performance in Network-on-Chip-Based Manycore Architectures
inferred← citeshttps://doi.org/10.1145/3695874openalex-snapshot
F-Bypass: A Low-Power Network-on-Chip Design Utilizing Bypass to Improve Network Connectivity
inferred← citeshttps://doi.org/10.1145/3842736openalex-snapshot
An Efficient Virtual Channel Power-Gating Method using Dynamic Bypass in NoC Routers
inferred← citeshttps://doi.org/10.3390/make8100296openalex-snapshot
Learning to Route On-Chip: A Survey of Machine Learning-Based Routing in Networks-on-Chip and Its Hardware Overheads
inferred← citeshttps://doi.org/10.37745/ejcsit.2013/vol13n41111120openalex-snapshot
Techniques for Optimizing Power, Performance, and Area (PPA) in Digital Design
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