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Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Improving Performance of OpenCL on CPUs
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Using the SSA-Form in a Code Generator
inferredcites →https://doi.org/10.1016/0096-0551(80)90007-7openalex-snapshot
Structural analysis: A new approach to flow analysis in optimizing compilers
inferredcites →https://doi.org/10.1109/40.865866openalex-snapshot
Implementing streaming SIMD extensions on the Pentium III processor
inferredcites →https://doi.org/10.1109/cgo.2011.5764682openalex-snapshot
Whole-function vectorization
inferredcites →https://doi.org/10.1109/cgo.2013.6494995openalex-snapshot
Convergence and scalarization for data-parallel architectures
inferredcites →https://doi.org/10.1109/iiswc.2009.5306797openalex-snapshot
Rodinia: A benchmark suite for heterogeneous computing
inferredcites →https://doi.org/10.1109/micro.1992.696999openalex-snapshot
Effective Compiler Support For Predicated Execution Using The Hyperblock
inferredcites →https://doi.org/10.1109/micro.1995.476825openalex-snapshot
Register allocation for predicated code
inferredcites →https://doi.org/10.1109/micro.2001.991116openalex-snapshot
Efficient static single assignment form for predication
inferredcites →https://doi.org/10.1109/mm.2008.31openalex-snapshot
NVIDIA Tesla: A Unified Graphics and Computing Architecture
inferredcites →https://doi.org/10.1109/mm.2009.9openalex-snapshot
Larrabee: A Many-Core x86 Architecture for Visual Computing
inferredcites →https://doi.org/10.1109/pact.2007.41openalex-snapshot
Introducing Control Flow into Vectorized Code
inferredcites →https://doi.org/10.1109/pact.2007.4336219openalex-snapshot
Introducing Control Flow into Vectorized Code
inferredcites →https://doi.org/10.1109/pact.2011.63openalex-snapshot
Divergence Analysis and Optimizations
inferredcites →https://doi.org/10.1145/1365490.1365500openalex-snapshot
Scalable Parallel Programming with CUDA
inferredcites →https://doi.org/10.1145/1401132.1401152openalex-snapshot
Scalable parallel programming with CUDA
inferredcites →https://doi.org/10.1145/144965.144998openalex-snapshot
Effective compiler support for predicated execution using the hyperblock
inferredcites →https://doi.org/10.1145/151333.151337openalex-snapshot
The transitive closure of control dependence
inferredcites →https://doi.org/10.1145/1772954.1772971openalex-snapshot
Efficient compilation of fine-grained SPMD-threaded programs for multicore CPUs
inferredcites →https://doi.org/10.1145/223982.225965openalex-snapshot
A comparison of full and partial predicated execution support for ILP processors
inferredcites →https://doi.org/10.1145/24039.24041openalex-snapshot
The program dependence graph and its use in optimization
inferredcites →https://doi.org/10.1145/2491464openalex-snapshot
Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators
inferredcites →https://doi.org/10.1145/2518037.2491464openalex-snapshot
Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators
inferredcites →https://doi.org/10.1145/339647.339693openalex-snapshot
Vector instruction set support for conditional operations
inferredcites →https://doi.org/10.1145/342001.339693openalex-snapshot
Vector instruction set support for conditional operations
inferredcites →https://doi.org/10.1145/567067.567085openalex-snapshot
Conversion of control dependence to data dependence
inferredcites →https://doi.org/10.5555/225160.225192openalex-snapshot
Register allocation for predicated code
inferredcites →https://doi.org/10.5555/243846.243868openalex-snapshot
Global predicate analysis and its application to register allocation
inferredcites →https://doi.org/10.5555/563998.564022openalex-snapshot
Efficient static single assignment form for predication
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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General-Purpose Graphics Processor Architectures
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DITVA: Dynamic Inter-Thread Vectorization Architecture
inferred← citeshttps://doi.org/10.1016/j.jpdc.2018.11.012openalex-snapshot
A survey of architectural approaches for improving GPGPU performance, programmability and heterogeneity
inferred← citeshttps://doi.org/10.1016/j.jpdc.2020.02.003openalex-snapshot
On-GPU thread-data remapping for nested branch divergence
inferred← citeshttps://doi.org/10.1016/j.sysarc.2017.03.001openalex-snapshot
Exploiting vectorization in high level synthesis of nested irregular loops
inferred← citeshttps://doi.org/10.1109/cgo51591.2021.9370326openalex-snapshot
Efficient Execution of Graph Algorithms on CPU with SIMD Extensions
inferred← citeshttps://doi.org/10.1109/hpcsim.2016.7568315openalex-snapshot
Efficient control flow restructuring for GPUs
inferred← citeshttps://doi.org/10.1109/micro20571.2012openalex-snapshot
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
inferred← citeshttps://doi.org/10.1109/sbac-pad.2016.11openalex-snapshot
Dynamic Inter-Thread Vectorization Architecture: Extracting DLP from TLP
inferred← citeshttps://doi.org/10.1109/seaa.2016.25openalex-snapshot
Analysing and Modelling the On-Chip Traffic of Parallel Applications
inferred← citeshttps://doi.org/10.1109/tcad.2015.2501303openalex-snapshot
An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization
inferred← citeshttps://doi.org/10.1145/2749469.2750375openalex-snapshot
Flexible software profiling of GPU architectures
inferred← citeshttps://doi.org/10.1145/2854038.2854041openalex-snapshot
gpucc: an open-source GPGPU compiler
inferred← citeshttps://doi.org/10.1145/2872887.2750375openalex-snapshot
Flexible software profiling of GPU architectures
inferred← citeshttps://doi.org/10.1145/3192366.3192368openalex-snapshot
CURD: a dynamic CUDA race detector
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Partial control-flow linearization
inferred← citeshttps://doi.org/10.1145/3296979.3192368openalex-snapshot
CURD: a dynamic CUDA race detector
inferred← citeshttps://doi.org/10.1145/3296979.3192413openalex-snapshot
Partial control-flow linearization
inferred← citeshttps://doi.org/10.1145/3559009.3569663openalex-snapshot
Combining Run-Time Checks and Compile-Time Analysis to Improve Control Flow Auto-Vectorization
inferred← citeshttps://doi.org/10.1145/3579990.3580019openalex-snapshot
Parsimony: Enabling SIMD/Vector Programming in Standard Compiler Flows
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Inside VOLT: Designing an Open-Source GPU Compiler (Tool)
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General-Purpose Graphics Processor Architectures
inferred← citeshttps://doi.org/10.5821/dissertation-2117-107939openalex-snapshot
Towards multiprogrammed GPUs
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