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DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11605805_1openalex-snapshot
Cache Attacks and Countermeasures: The Case of AES
inferredcites →https://doi.org/10.1007/11894063_16openalex-snapshot
Cache-Collision Timing Attacks Against AES
inferredcites →https://doi.org/10.1007/3-540-68697-5_9openalex-snapshot
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
inferredcites →https://doi.org/10.1007/978-3-319-11379-1_15openalex-snapshot
Wait a Minute! A fast, Cross-VM Attack on AES
inferredcites →https://doi.org/10.1007/978-3-319-40667-1_14openalex-snapshot
Flush+Flush: A Fast and Stealthy Cache Attack
inferredcites →https://doi.org/10.1007/978-3-642-23822-2_20openalex-snapshot
Remote Timing Attacks Are Still Practical
inferredcites →https://doi.org/10.1016/j.comnet.2005.01.010openalex-snapshot
Remote timing attacks are practical
inferredcites →https://doi.org/10.1109/cgo.2017.7863743openalex-snapshot
Optimizing function placement for large-scale data-center applications
inferredcites →https://doi.org/10.1109/hpca.2008.4658653openalex-snapshot
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems
inferredcites →https://doi.org/10.1109/hpca.2014.6835932openalex-snapshot
Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs
inferredcites →https://doi.org/10.1109/hpca.2015.7056045openalex-snapshot
High performing cache hierarchies for server workloads: Relaxing inclusion to capture the latency benefits of exclusive caches
inferredcites →https://doi.org/10.1109/hpca.2016.7446082openalex-snapshot
CATalyst: Defeating last-level cache side channel attacks in cloud computing
inferredcites →https://doi.org/10.1109/hpca.2016.7446102openalex-snapshot
Cache QoS: From concept to reality in the Intel® Xeon® processor E5-2600 v3 product family
inferredcites →https://doi.org/10.1109/hpca.2018.00019openalex-snapshot
KPart: A Hybrid Cache Partitioning-Sharing Technique for Commodity Multicores
inferredcites →https://doi.org/10.1109/hpca.2018.00024openalex-snapshot
Are Coherence Protocol States Vulnerable to Information Leakage?
inferredcites →https://doi.org/10.1109/iiswc.2015.12openalex-snapshot
Locality Exists in Graph Processing: Workload Characterization on an Ivy Bridge Server
inferredcites →https://doi.org/10.1109/sp.2015.43openalex-snapshot
Last-Level Cache Side-Channel Attacks are Practical
inferredcites →https://doi.org/10.1109/sp.2015.45openalex-snapshot
Controlled-Channel Attacks: Deterministic Side Channels for Untrusted Operating Systems
inferredcites →https://doi.org/10.1109/sp.2019.00002openalex-snapshot
Spectre Attacks: Exploiting Speculative Execution
inferredcites →https://doi.org/10.1137/1.9781611972740.43openalex-snapshot
R-MAT: A Recursive Model for Graph Mining
inferredcites →https://doi.org/10.1145/1060289.1060307openalex-snapshot
Memory resource management in VMware ESX server
inferredcites →https://doi.org/10.1145/1250662.1250709openalex-snapshot
Adaptive insertion policies for high performance caching
inferredcites →https://doi.org/10.1145/1250662.1250723openalex-snapshot
New cache designs for thwarting software cache-based side channel attacks
inferredcites →https://doi.org/10.1145/138873.138876openalex-snapshot
Page placement algorithms for large real-indexed caches
inferredcites →https://doi.org/10.1145/1456508.1456514openalex-snapshot
Deconstructing new cache designs for thwarting software cache-based side channel attacks
inferredcites →https://doi.org/10.1145/1519065.1519076openalex-snapshot
Towards practical page coloring-based multicore cache management
inferredcites →https://doi.org/10.1145/1815961.1815971openalex-snapshot
High performance cache replacement using re-reference interval prediction (RRIP)
inferredcites →https://doi.org/10.1145/2749469.2750392openalex-snapshot
Profiling a warehouse-scale computer
inferredcites →https://doi.org/10.1145/2830772.2830773openalex-snapshot
Large pages and lightweight memory management in virtualized environments
inferredcites →https://doi.org/10.1145/285930.285987openalex-snapshot
A low-overhead coherence solution for multiprocessors with private cache memories
inferredcites →https://doi.org/10.1145/3079856.3080222openalex-snapshot
Secure Hierarchy-Aware Cache Replacement Policy (SHARP)
inferredcites →https://doi.org/10.1145/325096.325161openalex-snapshot
The TLB slice—a low-cost high-speed address translation mechanism
inferredcites →https://doi.org/10.1145/773453.808204openalex-snapshot
A low-overhead coherence solution for multiprocessors with private cache memories
inferredcites →https://doi.org/10.1145/844128.844146openalex-snapshot
Memory resource management in VMware ESX server
inferredcites →https://doi.org/10.48550/arxiv.1502.07373openalex-snapshot
The Spy in the Sandbox -- Practical Cache Attacks in Javascript
inferredcites →https://doi.org/10.48550/arxiv.1708.09538openalex-snapshot
A Novel Scheduling Framework Leveraging Hardware Cache Partitioning for Cache-Side-Channel Elimination in Clouds
inferredcites →https://doi.org/10.48550/arxiv.1802.03802openalex-snapshot
MeltdownPrime and SpectrePrime: Automatically-Synthesized Attacks Exploiting Invalidation-Based Coherence Protocols
inferredcites →https://doi.org/10.48550/arxiv.1807.03757openalex-snapshot
Speculative Buffer Overflows: Attacks and Defenses
inferredcites →https://doi.org/10.5555/3049832.3049858openalex-snapshot
Optimizing function placement for large-scale data-center applications
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-58201-2_3openalex-snapshot
IE-Cache: Counteracting Eviction-Based Cache Side-Channel Attacks Through Indirect Eviction
inferred← citeshttps://doi.org/10.1007/978-3-030-60939-9_17openalex-snapshot
CHASM: Security Evaluation of Cache Mapping Schemes
inferred← citeshttps://doi.org/10.1007/978-3-030-62707-2_1openalex-snapshot
CIST: A Threat Modelling Approach for Hardware Supply Chain Security
inferred← citeshttps://doi.org/10.1007/978-3-030-80825-9_8openalex-snapshot
Specularizer : Detecting Speculative Execution Attacks via Performance Tracing
inferred← citeshttps://doi.org/10.1007/978-3-030-90870-6_3openalex-snapshot
Verifying Secure Speculation in Isabelle/HOL
inferred← citeshttps://doi.org/10.1007/978-3-030-97348-3_13openalex-snapshot
Under the Dome: Preventing Hardware Timing Information Leakage
inferred← citeshttps://doi.org/10.1007/978-3-031-20974-1_9openalex-snapshot
HyperDetector: Detecting, Isolating, and Mitigating Timing Attacks in Virtualized Environments
inferred← citeshttps://doi.org/10.1007/978-3-031-21637-4_2openalex-snapshot
Toward Secure VMs Allocation: Analysis of VMs Allocation Behaviours in the Cloud Computing Environments
inferred← citeshttps://doi.org/10.1007/978-3-031-45395-3_8openalex-snapshot
Microarchitectural Vulnerabilities Introduced, Exploited, and Accelerated by Heterogeneous FPGA-CPU Platforms
inferred← citeshttps://doi.org/10.1007/978-3-031-46479-9_1openalex-snapshot
Cybersecurity Landscape for Computer Systems
inferred← citeshttps://doi.org/10.1007/978-3-031-46479-9_4openalex-snapshot
Spectre and Meltdown Detection Using Explainable AI
inferred← citeshttps://doi.org/10.1007/978-3-031-50521-8_14openalex-snapshot
Automatic and Incremental Repair for Speculative Information Leaks
inferred← citeshttps://doi.org/10.1007/978-3-031-80020-7_1openalex-snapshot
Microarchitectural Security of Firecracker VMM for Serverless Cloud Platforms
inferred← citeshttps://doi.org/10.1007/978-3-031-84100-2_32openalex-snapshot
fence.t.s: Closing Timing Channels in High-Performance Out-of-Order Cores Through ISA-Supported Temporal Partitioning
inferred← citeshttps://doi.org/10.1007/978-3-031-93254-0_8openalex-snapshot
S-TSG: Description Model of Transient Execution Attacks in Intel SGX
inferred← citeshttps://doi.org/10.1007/978-3-031-98682-6_21openalex-snapshot
$$\mathbf{{\textsc {PyCaliper}}}$$: Python-Embedded Infrastructure for RTL Verification and Specification Synthesis
inferred← citeshttps://doi.org/10.1007/978-3-032-00627-1_6openalex-snapshot
Fast and Efficient Secure L1 Caches for SMT
inferred← citeshttps://doi.org/10.1007/978-3-032-00627-1_9openalex-snapshot
Exploring Speculation Barriers for RISC-V Selective Speculation
inferred← citeshttps://doi.org/10.1007/978-3-662-64322-8_14openalex-snapshot
Specfuscator: Evaluating Branch Removal as a Spectre Mitigation
inferred← citeshttps://doi.org/10.1007/978-981-15-1675-7_7openalex-snapshot
Cache Based Side-Channel Attacks
inferred← citeshttps://doi.org/10.1007/978-981-15-6401-7_10-1openalex-snapshot
Secure Processor Architectures
inferred← citeshttps://doi.org/10.1007/978-981-97-9314-3_10openalex-snapshot
Secure Processor Architectures
inferred← citeshttps://doi.org/10.1007/s10207-023-00669-zopenalex-snapshot
Secure cloud-based mobile apps: attack taxonomy, requirements, mechanisms, tests and automation
inferred← citeshttps://doi.org/10.1007/s11390-021-1249-4openalex-snapshot
Secure Speculation via Speculative Secret Flow Tracking
inferred← citeshttps://doi.org/10.1007/s41635-019-00075-9openalex-snapshot
Analysis of Secure Caches Using a Three-Step Model for Timing-Based Attacks
inferred← citeshttps://doi.org/10.1016/j.is.2020.101524openalex-snapshot
Winter is here! A decade of cache-based side-channel attacks, detection & mitigation for RSA
inferred← citeshttps://doi.org/10.1016/j.microrel.2021.114085openalex-snapshot
Verifying cache architecture vulnerabilities using a formal security verification flow
inferred← citeshttps://doi.org/10.1016/j.sysarc.2019.101698openalex-snapshot
FLUSH + PREFETCH: A countermeasure against access-driven cache-based side-channel attacks
inferred← citeshttps://doi.org/10.1016/j.sysarc.2024.103107openalex-snapshot
SecurityCloak: Protection against cache timing and speculative memory access attacks
inferred← citeshttps://doi.org/10.1016/j.vlsi.2020.02.004openalex-snapshot
A survey on attack vectors in stack cache memory
inferred← citeshttps://doi.org/10.1051/matecconf/202235503054openalex-snapshot
A novel cache based on dynamic mapping against speculative execution attacks
inferred← citeshttps://doi.org/10.1109/access.2020.3027946openalex-snapshot
Defending Against Flush+Reload Attack With DRAM Cache by Bypassing Shared SRAM Cache
inferred← citeshttps://doi.org/10.1109/access.2021.3085395openalex-snapshot
Multibyte Microarchitectural Data Sampling and its Application to Session Key Extraction Attacks
inferred← citeshttps://doi.org/10.1109/access.2023.3275757openalex-snapshot
Microarchitectural Side-Channel Threats, Weaknesses and Mitigations: A Systematic Mapping Study
inferred← citeshttps://doi.org/10.1109/access.2024.3424420openalex-snapshot
PEEV: Parse Encrypt Execute Verify—A Verifiable FHE Framework
inferred← citeshttps://doi.org/10.1109/access.2025.3555139openalex-snapshot
A Decade in Software-Based Side and Covert Channel Attacks and Countermeasures: A Survey
inferred← citeshttps://doi.org/10.1109/access.2025.3573038openalex-snapshot
Timing and Speculative Execution Attacks: Defeating State-of-the-Art Code-Reuse Defenses
inferred← citeshttps://doi.org/10.1109/acssc.2018.8645322openalex-snapshot
A Noise-resilient Detection Method against Advanced Cache Timing Channel Attack
inferred← citeshttps://doi.org/10.1109/asianhost51057.2020.9358255openalex-snapshot
Hardware-Based Detection of Spectre Attacks: A Machine Learning Approach
inferred← citeshttps://doi.org/10.1109/asp-dac52403.2022.9712560openalex-snapshot
CacheGuard: A Behavior Model Checker for Cache Timing Side-Channel Security: (Invited Paper)
inferred← citeshttps://doi.org/10.1109/cscwd61410.2024.10580256openalex-snapshot
KSM: Killer of Spectre and Meltdown Attacks
inferred← citeshttps://doi.org/10.1109/csf.2019.00027openalex-snapshot
A Formal Approach to Secure Speculation
inferred← citeshttps://doi.org/10.1109/dac63849.2025.11133121openalex-snapshot
ZION: A Practical Confidential Virtual Machine Architecture on Commodity RISC-V Processors
inferred← citeshttps://doi.org/10.1109/ddecs50862.2020.9095707openalex-snapshot
A Security Verification Template to Assess Cache Architecture Vulnerabilities
inferred← citeshttps://doi.org/10.1109/dsc47296.2019.8937682openalex-snapshot
Defeating Speculative-Execution Attacks on SGX with HyperRace
inferred← citeshttps://doi.org/10.1109/dsd51259.2020.00043openalex-snapshot
SCAAT: Secure Cache Alternative Address Table for mitigating cache logical side-channel attacks
inferred← citeshttps://doi.org/10.1109/dsn53405.2022.00052openalex-snapshot
TimeDice: Schedulability-Preserving Priority Inversion for Mitigating Covert Timing Channels Between Real-time Partitions
inferred← citeshttps://doi.org/10.1109/eurosp51992.2021.00040openalex-snapshot
SoK: Secure FPGA Multi-Tenancy in the Cloud: Challenges and Opportunities
inferred← citeshttps://doi.org/10.1109/eurosp51992.2021.00048openalex-snapshot
Bypassing memory safety mechanisms through speculative control flow hijacks
inferred← citeshttps://doi.org/10.1109/eurosp57164.2023.00044openalex-snapshot
SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations
inferred← citeshttps://doi.org/10.1109/fit57066.2022.00052openalex-snapshot
Let's Prevent Spectre Attacks in the Docker Containers Too
inferred← citeshttps://doi.org/10.1109/host49136.2021.9702278openalex-snapshot
Automated Detection of Spectre and Meltdown Attacks Using Explainable Machine Learning
inferred← citeshttps://doi.org/10.1109/host55118.2023.10133713openalex-snapshot
SCALE: Secure and Scalable Cache Partitioning
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Conditional Speculation: An Effective Approach to Safeguard Out-of-Order Execution Against Spectre Attacks
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00019openalex-snapshot
IRONHIDE: A Secure Multicore that Efficiently Mitigates Microarchitecture State Attacks for Interactive Applications
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00020openalex-snapshot
A New Side-Channel Vulnerability on Modern Computers by Exploiting Electromagnetic Emanations from the Power Management Unit
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Leaking Information Through Cache LRU States
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00014openalex-snapshot
New Models for Understanding and Reasoning about Speculative Execution Attacks
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00013openalex-snapshot
Leaky Frontends: Security Vulnerabilities in Processor Frontends
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00015openalex-snapshot
Abusing Cache Line Dirty States to Leak Information in Commercial Processors
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10070947openalex-snapshot
AutoCAT: Reinforcement Learning for Automated Exploration of Cache-Timing Attacks
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Modeling, Derivation, and Automated Analysis of Branch Predictor Security Vulnerabilities
inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408570openalex-snapshot
Protean: A Programmable Spectre Defense
inferred← citeshttps://doi.org/10.1109/hpcc-dss-smartcity-dependsys53884.2021.00121openalex-snapshot
StatekeepSpec: Securing Speculative Execution via forbidding Change-Of-State
inferred← citeshttps://doi.org/10.1109/hpec49654.2021.9622848openalex-snapshot
Timing-based side-channel attack and mitigation on PCIe connected distributed embedded systems
inferred← citeshttps://doi.org/10.1109/hpec62836.2024.10938520openalex-snapshot
IOS: A Low Cost Defense to Mitigate Meltdown and Spectre Like Attacks
inferred← citeshttps://doi.org/10.1109/hst.2019.8740835openalex-snapshot
COTSknight: Practical Defense against Cache Timing Channel Attacks using Cache Monitoring and Partitioning Technologies
inferred← citeshttps://doi.org/10.1109/iccad66269.2025.11240638openalex-snapshot
SpectrePrefetch: Undermining Cache-Centric Secure Speculation with Modern Hardware Prefetchers
inferred← citeshttps://doi.org/10.1109/iccad66269.2025.11241011openalex-snapshot
CacheGuardian: A Timing Side-Channel Resilient LLC Design
inferred← citeshttps://doi.org/10.1109/iiswc55918.2022.00011openalex-snapshot
PInTE: Probabilistic Induction of Theft Evictions
inferred← citeshttps://doi.org/10.1109/iiswc66894.2025.00024openalex-snapshot
CASM: A Generalizable and Accessible Security Metric to Evaluate Security of Cache Architectures
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00022openalex-snapshot
MuonTrap: Preventing Cross-Domain Spectre-Like Attacks by Capturing Speculative State
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00064openalex-snapshot
Speculative Data-Oblivious Execution: Mobilizing Safe Prediction For Safe and Efficient Speculative Execution
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00065openalex-snapshot
Packet Chasing: Spying on Network Packets over a Cache Side-Channel
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00067openalex-snapshot
A Bus Authentication and Anti-Probing Architecture Extending Hardware Trusted Computing Base Off CPU Chips and Beyond
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Zero Inclusion Victim: Isolating Core Caches from Inclusive Last-level Cache Evictions
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00035openalex-snapshot
Opening Pandora’s Box: A Systematic Study of New Ways Microarchitecture Can Leak Private Data
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00036openalex-snapshot
I See Dead µops: Leaking Secrets via Intel/AMD Micro-Op Caches
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00037openalex-snapshot
TimeCache: Using Time to Eliminate Cache Side Channels when Sharing Software
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00073openalex-snapshot
INTROSPECTRE: A Pre-Silicon Framework for Discovery and Analysis of Transient Execution Vulnerabilities
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00013openalex-snapshot
The Maya Cache: A Storage-efficient and Secure Fully-associative Last-level Cache
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00056openalex-snapshot
MetaLeak: Uncovering Side Channels in Secure Processor Architectures Exploiting Metadata
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00059openalex-snapshot
Perspective: A Principled Framework for Pliable and Secure Speculation in Operating Systems
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00045openalex-snapshot
Helium: Quantifying Microarchitectural Side-Channel Leakage with Probabilistic Guarantees
inferred← citeshttps://doi.org/10.1109/ispa-bdcloud-socialcom-sustaincom59178.2023.00089openalex-snapshot
DPFCFI: A Hardware-Based Forward Control-Flow Integrity for Architecture and Microarchitecture
inferred← citeshttps://doi.org/10.1109/isqed48828.2020.9137008openalex-snapshot
Entropy-Shield:Side-Channel Entropy Maximization for Timing-based Side-Channel Attacks
inferred← citeshttps://doi.org/10.1109/isqed51717.2021.9424259openalex-snapshot
Defending Against Misspeculation-based Cache Probe Attacks Using Variable Record Table
inferred← citeshttps://doi.org/10.1109/lca.2019.2916328openalex-snapshot
Isolating Speculative Data to Prevent Transient Execution Attacks
inferred← citeshttps://doi.org/10.1109/lca.2021.3112180openalex-snapshot
DAMARU: A Denial-of-Service Attack on Randomized Last-Level Caches
inferred← citeshttps://doi.org/10.1109/lca.2023.3289710openalex-snapshot
Guard Cache: Creating Noisy Side-Channels
inferred← citeshttps://doi.org/10.1109/lca.2025.3544989openalex-snapshot
Thor: A Non-Speculative Value Dependent Timing Side Channel Attack Exploiting Intel AMX
inferred← citeshttps://doi.org/10.1109/lca.2025.3555183openalex-snapshot
Exploiting Intel AMX Power Gating
inferred← citeshttps://doi.org/10.1109/mass52906.2021.00087openalex-snapshot
Hardware Speculation Vulnerabilities and Mitigations
inferred← citeshttps://doi.org/10.1109/mc.2025.3573841openalex-snapshot
Specification and Formal Verification of Hardware–Software Contracts for High-Assurance Computer Architectures
inferred← citeshttps://doi.org/10.1109/mcsoc51149.2021.00039openalex-snapshot
Detection of Cache Side Channel Attacks Using Thread Level Monitoring of Hardware Performance Counters
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00092openalex-snapshot
CaSA: End-to-end Quantitative Security Analysis of Randomly Mapped Caches
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00093openalex-snapshot
PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00094openalex-snapshot
Speculation Invariance (InvarSpec): Faster Safe Execution Through Program Analysis
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00045openalex-snapshot
RTL2MμPATH: Multi-μPATH Synthesis with Applications to Hardware Security Verification
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00087openalex-snapshot
IvLeague: Side Channel-Resistant Secure Architectures Using Isolated Domains of Dynamic Integrity Trees
inferred← citeshttps://doi.org/10.1109/milcom52596.2021.9652991openalex-snapshot
SCAMS: A Novel Side-Channel Attack Mitigation System in IaaS Cloud
inferred← citeshttps://doi.org/10.1109/mm.2019.2920814openalex-snapshot
Leveraging Cache Management Hardware for Practical Defense Against Cache Timing Channel Attacks
inferred← citeshttps://doi.org/10.1109/mm.2020.2985359openalex-snapshot
Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data
inferred← citeshttps://doi.org/10.1109/mm.2020.2986204openalex-snapshot
MicroScope: Enabling Microarchitectural Replay Attacks
inferred← citeshttps://doi.org/10.1109/mm.2021.3069158openalex-snapshot
Leaking Secrets Through Compressed Caches
inferred← citeshttps://doi.org/10.1109/msec.2019.2963021openalex-snapshot
SgxPectre: Stealing Intel Secrets From SGX Enclaves via Speculative Execution
inferred← citeshttps://doi.org/10.1109/msec.2020.2994978openalex-snapshot
With Great Complexity Comes Great Vulnerability: From Stand-Alone Fixes to Reconfigurable Security
inferred← citeshttps://doi.org/10.1109/pact.2019.00020openalex-snapshot
SpecShield: Shielding Speculative Data from Microarchitectural Covert Channels
inferred← citeshttps://doi.org/10.1109/sbac-pad63648.2024.00027openalex-snapshot
S-Clflush: Securing Against Flush-based Cache Timing Side-Channel Attacks
inferred← citeshttps://doi.org/10.1109/secdev45635.2020.00029openalex-snapshot
ReViCe: Reusing Victim Cache to Prevent Speculative Cache Leakage
inferred← citeshttps://doi.org/10.1109/seed51797.2021.00012openalex-snapshot
Seeds of SEED: A Side-Channel Resilient Cache Skewed by a Linear Function over a Galois Field
inferred← citeshttps://doi.org/10.1109/seed51797.2021.00013openalex-snapshot
Seeds of SEED: R-SAW: New Side Channels Exploiting Read Asymmetry in MLC Phase Change Memories
inferred← citeshttps://doi.org/10.1109/seed51797.2021.00014openalex-snapshot
Seeds of SEED: H2Cache: Building a Hybrid Randomized Cache Hierarchy for Mitigating Cache Side-Channel Attacks
inferred← citeshttps://doi.org/10.1109/seed51797.2021.00015openalex-snapshot
Bespoke Cache Enclaves: Fine-Grained and Scalable Isolation from Cache Side-Channels via Flexible Set-Partitioning
inferred← citeshttps://doi.org/10.1109/seed51797.2021.00023openalex-snapshot
SoK: Hardware Defenses Against Speculative Execution Attacks
inferred← citeshttps://doi.org/10.1109/seed55351.2022.00008openalex-snapshot
Avenger: Punishing the Cross-Core Last-Level Cache Attacker and Not the Victim by Isolating the Attacker
inferred← citeshttps://doi.org/10.1109/seed55351.2022.00011openalex-snapshot
These Aren’t The Caches You’re Looking For: Stochastic Channels on Randomized Caches
inferred← citeshttps://doi.org/10.1109/seed55351.2022.00012openalex-snapshot
Data-Out Instruction-In (DOIN!): Leveraging Inclusive Caches to Attack Speculative Delay Schemes
inferred← citeshttps://doi.org/10.1109/seed55351.2022.00023openalex-snapshot
Eliminating Micro-Architectural Side-Channel Attacks using Near Memory Processing
inferred← citeshttps://doi.org/10.1109/seed55351.2022.00024openalex-snapshot
Protecting On-Chip Data Access Against Timing-Based Side-Channel Attacks on Multicores
inferred← citeshttps://doi.org/10.1109/seed61283.2024.00015openalex-snapshot
INTERFACE: An Indirect, Partitioned, Random, Fully-Associative Cache to Avoid Shared Last-Level Cache Attacks
inferred← citeshttps://doi.org/10.1109/socc58585.2023.10256845openalex-snapshot
M-Party: A Secure Dynamic Cache Partitioning by More Than Two Parties
inferred← citeshttps://doi.org/10.1109/sp.2019.00047openalex-snapshot
The Code That Never Ran: Modeling Attacks on Speculative Evaluation
inferred← citeshttps://doi.org/10.1109/sp40000.2020.00033openalex-snapshot
SpecCFI: Mitigating Spectre Attacks using CFI Informed Speculation
inferred← citeshttps://doi.org/10.1109/sp40001.2021.00011openalex-snapshot
Systematic Analysis of Randomization-based Protected Cache Architectures
inferred← citeshttps://doi.org/10.1109/sp40001.2021.00036openalex-snapshot
Hardware-Software Contracts for Secure Speculation
inferred← citeshttps://doi.org/10.1109/sp46214.2022.9833570openalex-snapshot
Augury: Using Data Memory-Dependent Prefetchers to Leak Data at Rest
inferred← citeshttps://doi.org/10.1109/sp46214.2022.9833692openalex-snapshot
Adversarial Prefetch: New Cross-Core Cache Side Channel Attacks
inferred← citeshttps://doi.org/10.1109/sp46214.2022.9833707openalex-snapshot
SoK: Practical Foundations for Software Spectre Defenses
inferred← citeshttps://doi.org/10.1109/sp46214.2022.9833794openalex-snapshot
MeshUp: Stateless Cache Side-channel Attack on CPU Mesh
inferred← citeshttps://doi.org/10.1109/sp54263.2024.00048openalex-snapshot
Serberus: Protecting Cryptographic Code from Spectres at Compile-Time
inferred← citeshttps://doi.org/10.1109/sp61157.2025.00008openalex-snapshot
Ceviche: Capability-Enhanced Secure Virtualization of Caches
inferred← citeshttps://doi.org/10.1109/svcc56964.2023.10165527openalex-snapshot
Guard Cache: Creating False Cache Hits and Misses To Mitigate Side-Channel Attacks
inferred← citeshttps://doi.org/10.1109/tc.2020.2996021openalex-snapshot
OPTIMUS: A Security-Centric Dynamic Hardware Partitioning Scheme for Processors that Prevent Microarchitecture State Attacks
inferred← citeshttps://doi.org/10.1109/tc.2020.2997555openalex-snapshot
Exploiting Security Dependence for Conditional Speculation Against Spectre Attacks
inferred← citeshttps://doi.org/10.1109/tc.2020.3011748openalex-snapshot
Built-in Security Computer: Deploying Security-First Architecture Using Active Security Processor
inferred← citeshttps://doi.org/10.1109/tc.2021.3059531openalex-snapshot
Leaking Information Through Cache LRU States in Commercial Processors and Secure Caches
inferred← citeshttps://doi.org/10.1109/tc.2022.3209922openalex-snapshot
Preventing Coherence State Side Channel Leaks Using TimeCache
inferred← citeshttps://doi.org/10.1109/tc.2022.3222083openalex-snapshot
Reverse-Engineering and Exploiting the Frontend Bus of Intel Processor
inferred← citeshttps://doi.org/10.1109/tc.2023.3254918openalex-snapshot
Information Leakage Attacks Exploiting Cache Replacement in Commercial Processors
inferred← citeshttps://doi.org/10.1109/tc.2024.3377891openalex-snapshot
Prefender: A Prefetching Defender Against Cache Side Channel Attacks as a Pretender
inferred← citeshttps://doi.org/10.1109/tcad.2020.3047976openalex-snapshot
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools
inferred← citeshttps://doi.org/10.1109/tcad.2021.3070243openalex-snapshot
Imitating Functional Operations for Mitigating Side-Channel Leakage
inferred← citeshttps://doi.org/10.1109/tcad.2022.3193325openalex-snapshot
Architecting the Autocuckoo Filter to Defend Against Cross-Core Cache Attacks
inferred← citeshttps://doi.org/10.1109/tcad.2023.3284290openalex-snapshot
SpecWands: An Efficient Priority-Based Scheduler Against Speculation Contention Attacks
inferred← citeshttps://doi.org/10.1109/tcad.2024.3448264openalex-snapshot
PreSIT: Predict Cryptography Computations in SGX-Style Integrity Trees
inferred← citeshttps://doi.org/10.1109/tcad.2025.3585078openalex-snapshot
Exploiting ARMeD Channels By Reverse Engineering ARM Memory Disambiguation Unit
inferred← citeshttps://doi.org/10.1109/tcc.2024.3383661openalex-snapshot
Space-Hard Obfuscation Against Shared Cache Attacks and its Application in Securing ECDSA for Cloud-Based Blockchains
inferred← citeshttps://doi.org/10.1109/tcsi.2023.3298913openalex-snapshot
PMU-Spill: A New Side Channel for Transient Execution Attacks
inferred← citeshttps://doi.org/10.1109/tdsc.2021.3089882openalex-snapshot
CBA-Detector: A Self-Feedback Detector Against Cache-Based Attacks
inferred← citeshttps://doi.org/10.1109/tdsc.2022.3144287openalex-snapshot
SpecBox: A Label-Based Transparent Speculation Scheme Against Transient Execution Attacks
inferred← citeshttps://doi.org/10.1109/tdsc.2022.3194871openalex-snapshot
Securing TEEs With Verifiable Execution Contracts
inferred← citeshttps://doi.org/10.1109/tdsc.2024.3354991openalex-snapshot
TreasureCache: Hiding Cache Evictions Against Side-Channel Attacks
inferred← citeshttps://doi.org/10.1109/tdsc.2025.3604008openalex-snapshot
Complementing Confidential Computing Environment for Applications on Arm CCA
inferred← citeshttps://doi.org/10.1109/tifs.2024.3368862openalex-snapshot
RECAST: Mitigating Conflict-Based Cache Attacks Through Fine-Grained Dynamic Mapping
inferred← citeshttps://doi.org/10.1109/tifs.2024.3414255openalex-snapshot
Write+Sync: Software Cache Write Covert Channels Exploiting Memory-Disk Synchronization
inferred← citeshttps://doi.org/10.1109/tifs.2026.3660599openalex-snapshot
HiveTEE: Scalable and Fine-Grained Isolated Domains With RME and MTE Co-Assisted
inferred← citeshttps://doi.org/10.1109/tps-isa67132.2025.00031openalex-snapshot
EDL: Efficient Data-Oblivious Loops
inferred← citeshttps://doi.org/10.1109/trustcom50675.2020.00018openalex-snapshot
SeRoT: A Secure Runtime System on Trusted Execution Environments
inferred← citeshttps://doi.org/10.1109/trustcom63139.2024.00132openalex-snapshot
TTFL: Towards Trustworthy Federated Learning with Arm Confidential Computing
inferred← citeshttps://doi.org/10.1109/tse.2019.2953709openalex-snapshot
oo7: Low-Overhead Defense Against Spectre Attacks via Program Analysis
inferred← citeshttps://doi.org/10.1117/12.3032005openalex-snapshot
Isolate cache shield: defending cache attacks via cache set isolation
inferred← citeshttps://doi.org/10.1142/s0218126623500263openalex-snapshot
Dynamic First Access Isolation Cache to Eliminate Reuse-Based Cache Side Channel Attacks
inferred← citeshttps://doi.org/10.1145/3307650.3322216openalex-snapshot
Efficient invisible speculative execution through selective delay and value prediction
inferred← citeshttps://doi.org/10.1145/3307650.3322246openalex-snapshot
New attacks and defense for encrypted-address cache
inferred← citeshttps://doi.org/10.1145/3361870openalex-snapshot
Exploiting Bank Conflict-based Side-channel Timing Leakage of GPUs
inferred← citeshttps://doi.org/10.1145/3373376.3378453openalex-snapshot
Safecracker: Leaking Secrets through Compressed Caches
inferred← citeshttps://doi.org/10.1145/3373376.3378510openalex-snapshot
A Benchmark Suite for Evaluating Caches' Vulnerability to Timing Attacks
inferred← citeshttps://doi.org/10.1145/3373376.3378526openalex-snapshot
Exploring Branch Predictors for Constructing Transient Execution Trojans
inferred← citeshttps://doi.org/10.1145/3385412.3386008openalex-snapshot
CacheQuery: learning replacement policies from hardware caches
inferred← citeshttps://doi.org/10.1145/3386263.3407584openalex-snapshot
Evolution of Defenses against Transient-Execution Attacks
inferred← citeshttps://doi.org/10.1145/3394885.3431638openalex-snapshot
Micro-architectural Cache Side-Channel Attacks and Countermeasures
inferred← citeshttps://doi.org/10.1145/3404397.3404434openalex-snapshot
First Time Miss : Low Overhead Mitigation for Shared Memory Cache Side Channels
inferred← citeshttps://doi.org/10.1145/3442479openalex-snapshot
Survey of Transient Execution Attacks and Their Mitigations
inferred← citeshttps://doi.org/10.1145/3445814.3446708openalex-snapshot
Speculative interference attacks: breaking invisible speculation schemes
inferred← citeshttps://doi.org/10.1145/3445814.3446742openalex-snapshot
Streamline: a fast, flushless cache covert-channel attack by enabling asynchronous collusion
inferred← citeshttps://doi.org/10.1145/3456299openalex-snapshot
Software-driven Security Attacks: From Vulnerability Sources to Durable Hardware Defenses
inferred← citeshttps://doi.org/10.1145/3456629openalex-snapshot
A Survey of Microarchitectural Side-channel Vulnerabilities, Attacks, and Defenses in Cryptography
inferred← citeshttps://doi.org/10.1145/3466752.3480068openalex-snapshot
Speculative Privacy Tracking (SPT): Leaking Information From Speculative Execution Without Compromising Privacy
inferred← citeshttps://doi.org/10.1145/3466752.3480079openalex-snapshot
UC-Check: Characterizing Micro-operation Caches in x86 Processors and Implications in Security and Performance
inferred← citeshttps://doi.org/10.1145/3471621.3471857openalex-snapshot
BasicBlocker: ISA Redesign to Make Spectre-Immune CPUs Faster
inferred← citeshttps://doi.org/10.1145/3472883.3487006openalex-snapshot
Provisioning Differentiated Last-Level Cache Allocations to VMs in Public Clouds
inferred← citeshttps://doi.org/10.1145/3485506openalex-snapshot
SpecSafe: detecting cache side channels in a speculative world
inferred← citeshttps://doi.org/10.1145/3494538openalex-snapshot
CASHT: Contention Analysis in Shared Hierarchies with Thefts
inferred← citeshttps://doi.org/10.1145/3503222.3507724openalex-snapshot
Pinned loads: taming speculative loads in secure processors
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