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Defeating UCI: Building Stealthy and Malicious Hardware
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-58179-0_44openalex-snapshot
Automatic verification of pipelined microprocessor control
inferredcites →https://doi.org/10.1007/978-3-642-03240-0_7openalex-snapshot
Fighting State Space Explosion: Review and Evaluation
inferredcites →https://doi.org/10.1007/978-3-642-15031-9_12openalex-snapshot
Self-referencing: A Scalable Side-Channel Approach for Hardware Trojan Detection
inferredcites →https://doi.org/10.1007/bfb0028737openalex-snapshot
Formal verification of out-of-order execution using incremental flushing
inferredcites →https://doi.org/10.1023/a:1024716316140openalex-snapshot
Formal Verification of a Complex Pipelined Processor
inferredcites →https://doi.org/10.1109/52.57892openalex-snapshot
Formal verification of a pipelined microprocessor
inferredcites →https://doi.org/10.1109/date.2010.5456930openalex-snapshot
Detecting/preventing information leakage on the memory bus due to malicious hardware
inferredcites →https://doi.org/10.1109/hst.2008.4559037openalex-snapshot
Sensitivity analysis to hardware Trojans using power supply transient signals
inferredcites →https://doi.org/10.1109/hst.2008.4559049openalex-snapshot
Hardware Trojan detection using path delay fingerprint
inferredcites →https://doi.org/10.1109/hst.2008.4559051openalex-snapshot
Verifying the authenticity of chip designs with the DesignTag system
inferredcites →https://doi.org/10.1109/hst.2009.5224971openalex-snapshot
Experiences in Hardware Trojan design and implementation
inferredcites →https://doi.org/10.1109/icvd.1999.745161openalex-snapshot
Formal verification of an ARM processor
inferredcites →https://doi.org/10.1109/mspec.2008.4505310openalex-snapshot
The Hunt For The Kill Switch
inferredcites →https://doi.org/10.1109/sp.2007.28openalex-snapshot
Moats and Drawbridges: An Isolation Primitive for Reconfigurable Hardware Based Systems
inferredcites →https://doi.org/10.1109/sp.2007.36openalex-snapshot
Trojan Detection using IC Fingerprinting
inferredcites →https://doi.org/10.1109/sp.2010.18openalex-snapshot
Overcoming an Untrusted Computing Base: Detecting and Removing Malicious Hardware Automatically
inferredcites →https://doi.org/10.1145/1837274.1837435openalex-snapshot
Synthesis of trustable ICs using untrusted CAD tools
inferredcites →https://doi.org/10.1145/1866307.1866335openalex-snapshot
Modeling attacks on physical unclonable functions
inferredcites →https://doi.org/10.1145/307988.307989openalex-snapshot
Formal verification in hardware design
inferredcites →https://doi.org/10.1145/337292.337331openalex-snapshot
Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction
inferredcites →https://doi.org/10.1145/586110.586132openalex-snapshot
Silicon physical random functions
inferredcites →https://doi.org/10.5555/1870926.1871135openalex-snapshot
Detecting/preventing information leakage on the memory bus due to malicious hardware
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Malicious IoT Implants: Tampering with Serial Communication over the Internet
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Security and Trust Verification of IoT SoCs
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SoC Security Verification Challenges
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SoC Trust Metrics and Benchmarks
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ProTro: A Probabilistic Counter Based Hardware Trojan Attack on FPGA Based MACSec Enabled Ethernet Switch
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Hardware Trojans in Microcircuits
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Countermeasures Against Hardware Trojans
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Hardware Trojan Localization: Modeling and Empirical Approach
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Hardware Trojan Detection
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Exploring Classic Security Attacks and Hardware Intricacies
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IP Trust Validation Using Proof-Carrying Hardware
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Hardware Trust Verification
inferred← citeshttps://doi.org/10.1007/978-3-319-49025-0_4openalex-snapshot
Code Coverage Analysis for IP Trust Verification
inferred← citeshttps://doi.org/10.1007/978-3-319-49025-0_9openalex-snapshot
Validation of IP Security and Trust
inferred← citeshttps://doi.org/10.1007/978-3-319-50057-7_2openalex-snapshot
Security Validation in Modern SoC Designs
inferred← citeshttps://doi.org/10.1007/978-3-319-50057-7_4openalex-snapshot
IP Trust: The Problem and Design/Validation-Based Solution
inferred← citeshttps://doi.org/10.1007/978-3-319-93659-8_91openalex-snapshot
A Method of Hardware-Trojan Detection Using Design Verification Techniques
inferred← citeshttps://doi.org/10.1007/978-3-642-39235-1_12openalex-snapshot
Preventing Backdoors in Server Applications with a Separated Software Architecture
inferred← citeshttps://doi.org/10.1007/978-981-10-7470-7_34openalex-snapshot
Defeating HaTCh: Building Malicious IP Cores
inferred← citeshttps://doi.org/10.1007/s10836-023-06071-wopenalex-snapshot
Multi-Objective Optimization Based Test Pattern Generation for Hardware Trojan Detection
inferred← citeshttps://doi.org/10.1007/s10836-023-06080-9openalex-snapshot
Structural and SCOAP Features Based Approach for Hardware Trojan Detection Using SHAP and Light Gradient Boosting Model
inferred← citeshttps://doi.org/10.1007/s13389-026-00404-zopenalex-snapshot
An explainable semi-supervised self-training approach for hardware Trojan detection using LIME
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Surveying the Hardware Trojan Threat Landscape for the Internet-of-Things
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The Old Frontier of Reverse Engineering: Netlist Partitioning
inferred← citeshttps://doi.org/10.1007/s41635-020-00100-2openalex-snapshot
A Framework for Hardware Trojan Vulnerability Estimation and Localization in RTL Designs
inferred← citeshttps://doi.org/10.1007/s41635-020-00107-9openalex-snapshot
Probabilistic Hardware Trojan Attacks on Multiple Layers of Reconfigurable Network Infrastructure
inferred← citeshttps://doi.org/10.1007/s41870-017-0011-1openalex-snapshot
A defense mechanism against hardware Trojan insertion by third-party intellectual property (IP) design blocks in AES-based secured communication system
inferred← citeshttps://doi.org/10.1016/b978-0-12-812477-2.00011-3openalex-snapshot
Electronics Supply Chain
inferred← citeshttps://doi.org/10.1016/j.asoc.2021.108068openalex-snapshot
Machine learning for hardware security: Classifier-based identification of Trojans in pipelined microprocessors
inferred← citeshttps://doi.org/10.1016/j.cose.2021.102223openalex-snapshot
Towards bidirectional LUT-level detection of hardware Trojans
inferred← citeshttps://doi.org/10.1016/j.mejo.2021.105023openalex-snapshot
A trojan framework in AES core to evade state-of-the-art HT detection schemes
inferred← citeshttps://doi.org/10.1016/j.vlsi.2016.03.002openalex-snapshot
VLSI supply chain security risks and mitigation techniques: A survey
inferred← citeshttps://doi.org/10.1016/j.vlsi.2016.10.014openalex-snapshot
IP protection through gate-level netlist security enhancement
inferred← citeshttps://doi.org/10.1049/cds2.12088openalex-snapshot
Blinding HT: Hiding Hardware Trojan signals traced across multiple sequential levels
inferred← citeshttps://doi.org/10.1049/iet-cdt.2020.0041openalex-snapshot
Ten years of hardware Trojans: a survey from the attacker's perspective
inferred← citeshttps://doi.org/10.1109/access.2019.2896479openalex-snapshot
A Multi-Layer Hardware Trojan Protection Framework for IoT Chips
inferred← citeshttps://doi.org/10.1109/access.2023.3288696openalex-snapshot
A Survey on Hardware Security: Current Trends and Challenges
inferred← citeshttps://doi.org/10.1109/access.2025.3555166openalex-snapshot
A Survey on the Design, Detection, and Prevention of Pre-Silicon Hardware Trojans
inferred← citeshttps://doi.org/10.1109/acsac63791.2024.00077openalex-snapshot
Evil from Within: Machine Learning Backdoors Through Dormant Hardware Trojans
inferred← citeshttps://doi.org/10.1109/aspdac.2016.7428086openalex-snapshot
Netlist reverse engineering for high-level functionality reconstruction
inferred← citeshttps://doi.org/10.1109/aspdac.2017.7858388openalex-snapshot
Trojan localization using symbolic algebra
inferred← citeshttps://doi.org/10.1109/ats.2016.45openalex-snapshot
Property Coverage Analysis Based Trustworthiness Verification for Potential Threats from EDA Tools
inferred← citeshttps://doi.org/10.1109/ccis63231.2024.10932003openalex-snapshot
Secure Federated Learning for Gate-Level IP Hardware Trojan Detection Using Homomorphic Encryption
inferred← citeshttps://doi.org/10.1109/date.2012.6176642openalex-snapshot
SAFER PATH: Security architecture using fragmented execution and replication for protection against trojaned hardware
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Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling
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Stealthy Trojan Detection Based on Feature Analysis of Circuit Structure
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Temperature-triggered behavioral IPs HW Trojan detection method with FPGAs
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Exploiting sub-graph isomorphism and probabilistic neural networks for the detection of hardware Trojans at RTL
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Reverse engineering circuits using behavioral pattern mining
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WordRev: Finding word-level structures in a sea of bit-level gates
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On hardware Trojan design and implementation at register-transfer level
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Hardware security: Threat models and metrics
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Why you should care about don't cares: Exploiting internal don't care conditions for hardware Trojans
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Trojan Detection using Convolutional Neural Network
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The Design of a Novel Hardware Trojan without Inactive Signal for AES
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AI-Powered Detection of Hardware Trojans in Integrated Circuits Using Side-Channel Analysis
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Formal Verification Approach to Detect Always-On Denial of Service Trojans in Pipelined Circuits
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A Survey on Recent Detection Methods of the Hardware Trojans
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A Survey on Recent Developments in SCOAP-based Hardware Trojan Detection Strategies
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Hardware Trojan Detection Based on Circuit Sequence Features with GRU Neural Network
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Using Path Features for Hardware Trojan Detection Based on Machine Learning Techniques
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Revisiting Trojan Insertion Techniques for Post-Silicon Trojan Detection Evaluation
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Reconstruction-Guided Graph Embedding for Unsupervised Trojan Detection
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Using outliers to detect stealthy hardware trojan triggering?
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Property Based Formal Security Verification for Hardware Trojan Detection
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A Primer on Hardware Security: Models, Methods, and Metrics
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Hardware Trojan with Frequency Modulation
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Securing Processors Against Insider Attacks: A Circuit-Microarchitecture Co-Design Approach
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Can the SHIELD protect our integrated circuits?
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Advancing the state-of-the-art in hardware Trojans design
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Enhanced Hardware Trojan Detection in Chips By Reducing Linearity Between Features
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Smart employment of circuit redundancy to effectively counter trojans (SECRET) in third-party IP cores
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Identifying Specious LUTs for Satisfiability Don’t Care Trojan Detection
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Hardware Security in the Internet of Things: A Survey
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A Framework to Eliminate Backdoors from Response-Computable Authentication
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True2F: Backdoor-Resistant Authentication Tokens
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Bomberman: Defining and Defeating Hardware Ticking Timebombs at Design-time
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Trojan Detection in Embedded Systems With FinFET Technology
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VeriTrust: Verification for Hardware Trust
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TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits
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Hardware Trojan Detection Using Graph Neural Networks
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TroLL: Exploiting Structural Similarities Between Logic Locking and Hardware Trojans
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Advancing the State-of-the-Art in Hardware Trojans Detection
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Hardware trojan detection through information flow security verification
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Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution
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Reverse Engineering Digital Circuits Using Structural and Functional Analyses
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Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security- Driven Task Scheduling
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Hardware Trojan Detection in Behavioral Intellectual Properties (IP's) Using Property Checking Techniques
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Gate Characterization Using Singular Value Decomposition: Foundations and Applications
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Eliminating the Hardware-Software Boundary: A Proof-Carrying Approach for Trust Evaluation on Computer Systems
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Trigger Identification Using Difference-Amplified Controllability and Dynamic Transition Probability for Hardware Trojan Detection
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A Game-Theoretic Approach for Testing for Hardware Trojans
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Novel Design of Hardware Trojan: A Generic Approach for Defeating Testability Based Detection
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Golden Reference-Free Hardware Trojan Localization Using Graph Convolutional Network
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Exploring Hard to Detect Sequential Hardware Trojans
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Trojan Localization Using Information Flow Tracking Properties in SoC Designs
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Towards reducing the attack surface of software backdoors
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Exploiting heterogeneity in MPSoCs to prevent potential trojan propagation across malicious IPs
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Trustworthy hardware from untrusted components
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Pre-silicon security verification and validation
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Efficient Control-Flow Subgraph Matching for Detecting Hardware Trojans in RTL Models
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Architectural Support for Containment-based Security
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ATTRITION: Attacking Static Hardware Trojan Detection Techniques Using Reinforcement Learning
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eXpect: On the Security Implications of Violations in AXI Implementations
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SeqCube-HT: state-cube-guided generation of sequential hardware Trojan benchmarks
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HaTCh: Hardware Trojan Catcher
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Holistic hardware Trojan design of trigger and payload at gate level with rare switching signals eliminated
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Hardware-Trojans Rank: Quantitative Evaluation of Security Threats at Gate-Level Netlists by Pattern Matching
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Formal Methods for Reverse Engineering Gate-Level Netlists
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Hardware Trojans. Part3: methods for prevention and detection
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A Golden-Free Formal Method for Trojan Detection in Non-Interfering Accelerators
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Xray: Detecting and Exploiting Vulnerabilities in Arm AXI Interconnects
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Introduction to Hardware Security
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Sequentially Triggering “Time-Bomb” Trojan into Hardware Wired Microsequencer
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Validation of Hardware Security and Trust: A Survey
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Boosting the Bounds of Symbolic QED for Effective Pre-Silicon Verification of Processor Cores
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TAAL: Tampering Attack on Any Key-based Logic Locked Circuits
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SAFER PATH: security architecture using fragmented execution and replication for protection against trojaned hardware
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Producing Trustworthy Hardware Using Untrusted Components, Personnel and Resources
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