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A Compiler Approach for Exploiting Partial SIMD Parallelism

https://doi.org/10.1145/2886101
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4615-4337-4openalex-snapshot
Loop Tiling for Parallelism
inferredcites →https://doi.org/10.1007/978-3-319-10936-7_20openalex-snapshot
Region-Based Selective Flow-Sensitive Pointer Analysis
inferredcites →https://doi.org/10.1007/978-3-540-45209-6_39openalex-snapshot
SIMD Vectorization of Straight Line FFT Code
inferredcites →https://doi.org/10.1007/978-3-658-10113-8openalex-snapshot
Automatic SIMD Vectorization of SSA-based Control Flow Graphs
inferredcites →https://doi.org/10.1023/a:1007559022013openalex-snapshot
A Vectorizing Compiler for Multimedia Extensions
inferredcites →https://doi.org/10.1023/a:1014230429447openalex-snapshot
Automatic Intra-Register Vectorization for the Intel® Architecture
inferredcites →https://doi.org/10.1109/cgo.2005.33openalex-snapshot
Superword-Level Parallelism in the Presence of Control Flow
inferredcites →https://doi.org/10.1109/cgo.2011.5764683openalex-snapshot
Vapor SIMD: Auto-vectorize once, run everywhere
inferredcites →https://doi.org/10.1109/cgo.2013.6494989openalex-snapshot
SIMD parallelization of applications that traverse irregular data structures
inferredcites →https://doi.org/10.1109/cgo20717.2013openalex-snapshot
Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)
inferredcites →https://doi.org/10.1109/icpp.1999openalex-snapshot
Proceedings of the 1999 International Conference on Parallel Processing
inferredcites →https://doi.org/10.1109/icpp.2003.1240630openalex-snapshot
Code tiling for improving the cache performance of PDE solvers
inferredcites →https://doi.org/10.1109/micro.2010.38openalex-snapshot
Efficient Selection of Vector Instructions Using Dynamic Programming
inferredcites →https://doi.org/10.1109/pact.2002.1105967openalex-snapshot
Proceedings 2002 International Conference on Parallel Architectures and Compilation Techniques. PACT 2002
inferredcites →https://doi.org/10.1109/pact.2003.1237995openalex-snapshot
Proceedings 12th International Conference on Parallel Architectures and Compilation Techniques - PACT 2003
inferredcites →https://doi.org/10.1109/pact.2007.41openalex-snapshot
Introducing Control Flow into Vectorized Code
inferredcites →https://doi.org/10.1109/pact.2009.18openalex-snapshot
Polyhedral-Model Guided Loop-Nest Auto-Vectorization
inferredcites →https://doi.org/10.1109/pact.2011.68openalex-snapshot
An Evaluation of Vectorizing Compilers
inferredcites →https://doi.org/10.1145/1088149.1088172openalex-snapshot
An integrated simdization framework using virtual vectors
inferredcites →https://doi.org/10.1145/1133255.1133996openalex-snapshot
Optimizing data permutations for SIMD devices
inferredcites →https://doi.org/10.1145/1133255.1133997openalex-snapshot
Auto-vectorization of interleaved data for SIMD
inferredcites →https://doi.org/10.1145/1133981.1133996openalex-snapshot
Optimizing data permutations for SIMD devices
inferredcites →https://doi.org/10.1145/1133981.1133997openalex-snapshot
Auto-vectorization of interleaved data for SIMD
inferredcites →https://doi.org/10.1145/1995896.1995938openalex-snapshot
Automatic SIMD vectorization of fast fourier transforms for the larrabee and AVX instruction sets
inferredcites →https://doi.org/10.1145/2145816.2145824openalex-snapshot
Efficient SIMD code generation for irregular kernels
inferredcites →https://doi.org/10.1145/2150976.2151014openalex-snapshot
SIMD defragmenter
inferredcites →https://doi.org/10.1145/2254064.2254106openalex-snapshot
A compiler framework for extracting superword level parallelism
inferredcites →https://doi.org/10.1145/2345156.2254106openalex-snapshot
A compiler framework for extracting superword level parallelism
inferredcites →https://doi.org/10.1145/2370036.2145824openalex-snapshot
Efficient SIMD code generation for irregular kernels
inferredcites →https://doi.org/10.1145/2491956.2462187openalex-snapshot
When polyhedral transformations meet SIMD code generation
inferredcites →https://doi.org/10.1145/2499370.2462187openalex-snapshot
When polyhedral transformations meet SIMD code generation
inferredcites →https://doi.org/10.1145/2854038.2854054openalex-snapshot
Exploiting mixed SIMD parallelism by reducing data reorganization overhead
inferredcites →https://doi.org/10.1145/305138.305231openalex-snapshot
Nonlinear array layouts for hierarchical memory systems
inferredcites →https://doi.org/10.1145/349299.349320openalex-snapshot
Exploiting superword level parallelism with multimedia instruction sets
inferredcites →https://doi.org/10.1145/358438.349320openalex-snapshot
Exploiting superword level parallelism with multimedia instruction sets
inferredcites →https://doi.org/10.1145/76263.76337openalex-snapshot
More iteration space tiling
inferredcites →https://doi.org/10.1145/996841.996853openalex-snapshot
Vectorization for SIMD architectures with alignment constraints
inferredcites →https://doi.org/10.5555/2523721.2523767openalex-snapshot
Breaking SIMD shackles with an exposed flexible microarchitecture and the access execute PDG
inferredcites →https://doi.org/10.5555/2523721.2523769openalex-snapshot
Vectorization past dependent branches through speculation
inferredcites →https://doi.org/10.5555/2523721.2523770openalex-snapshot
Automatic vectorization of tree traversals
inferredcites →https://doi.org/10.5555/2738600.2738625openalex-snapshot
PSLP: padded SLP automatic vectorization
inferredcites →https://doi.org/10.5555/645989.674329openalex-snapshot
Increasing and detecting memory address congruence

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/spe.2573openalex-snapshot
Efficient and retargetable SIMD translation in a dynamic binary translator
inferred← citeshttps://doi.org/10.1007/978-3-030-72789-5_2openalex-snapshot
PostSLP: Cross-Region Vectorization of Fully or Partially Vectorized Code
inferred← citeshttps://doi.org/10.1007/s10586-024-05057-3openalex-snapshot
Parallel optimization techniques for ultra-large scale refined numerical simulations on Chinese supercomputers
inferred← citeshttps://doi.org/10.1016/j.sysarc.2019.07.008openalex-snapshot
Optimizing data permutations in structured loads/stores translation and SIMD register mapping for a cross-ISA dynamic binary translator
inferred← citeshttps://doi.org/10.1063/5.0264977openalex-snapshot
Compiler simulation for learning multiprocessor computers on a single instruction stream
inferred← citeshttps://doi.org/10.1109/ase63991.2025.00147openalex-snapshot
HybridSIMD: A Super C++ SIMD Library with Integrated Auto-tuning Capabilities
inferred← citeshttps://doi.org/10.1109/cgo.2017.7863734openalex-snapshot
Automatic generation of fast BLAS3-GEMM: A portable compiler approach
inferred← citeshttps://doi.org/10.1109/cgo.2019.8661192openalex-snapshot
Super-Node SLP: Optimized Vectorization for Code Sequences Containing Operators and Their Inverse Elements
inferred← citeshttps://doi.org/10.1109/cgo57630.2024.10444841openalex-snapshot
PresCount: Effective Register Allocation for Bank Conflict Reduction
inferred← citeshttps://doi.org/10.1109/cinti.2016.7846386openalex-snapshot
Improving performance and energy consumption with loop fusion optimization and parallelization
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10070941openalex-snapshot
High Performance and Power Efficient Accelerator for Cloud Inference
inferred← citeshttps://doi.org/10.1109/iccp.2017.8117057openalex-snapshot
An implementation of loop fusion for improving performance and energy consumption of shared-memory parallel codes
inferred← citeshttps://doi.org/10.1109/llvm-hpc.2018.8639483openalex-snapshot
Function/Kernel Vectorization via Loop Vectorizer
inferred← citeshttps://doi.org/10.1109/pact.2017.15openalex-snapshot
Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation
inferred← citeshttps://doi.org/10.1109/pact.2017.21openalex-snapshot
SuperGraph-SLP Auto-Vectorization
inferred← citeshttps://doi.org/10.1145/2907950.2907957openalex-snapshot
Loop-oriented array- and field-sensitive pointer analysis for automatic SIMD vectorization
inferred← citeshttps://doi.org/10.1145/2980930.2907957openalex-snapshot
Loop-oriented array- and field-sensitive pointer analysis for automatic SIMD vectorization
inferred← citeshttps://doi.org/10.1145/3078633.3081029openalex-snapshot
Dynamic translation of structured Loads/Stores and register mapping for architectures with SIMD extensions
inferred← citeshttps://doi.org/10.1145/3123939.3124554openalex-snapshot
Improving the effectiveness of searching for isomorphic chains in superword level parallelism
inferred← citeshttps://doi.org/10.1145/3140582.3081029openalex-snapshot
Dynamic translation of structured Loads/Stores and register mapping for architectures with SIMD extensions
inferred← citeshttps://doi.org/10.1145/3168364openalex-snapshot
Loop-Oriented Pointer Analysis for Automatic SIMD Vectorization
inferred← citeshttps://doi.org/10.1145/3168807openalex-snapshot
Look-ahead SLP: auto-vectorization in the presence of commutative operations
inferred← citeshttps://doi.org/10.1145/3168808openalex-snapshot
Poker: permutation-based SIMD execution of intensive tree search by path encoding
inferred← citeshttps://doi.org/10.1145/3173456openalex-snapshot
Improving SIMD Parallelism via Dynamic Binary Translation
inferred← citeshttps://doi.org/10.1145/3243176.3243189openalex-snapshot
VW-SLP
inferred← citeshttps://doi.org/10.1145/3274654openalex-snapshot
SCP
inferred← citeshttps://doi.org/10.1145/3280850openalex-snapshot
P oker
inferred← citeshttps://doi.org/10.1145/3301488openalex-snapshot
Exploiting SIMD Asymmetry in ARM-to-x86 Dynamic Binary Translation
inferred← citeshttps://doi.org/10.1145/3302516.3307350openalex-snapshot
PPOpenCL: a performance-portable OpenCL compiler with host and kernel thread code fusion
inferred← citeshttps://doi.org/10.1145/3373087.3375296openalex-snapshot
Flexible Communication Avoiding Matrix Multiplication on FPGA with High-Level Synthesis
inferred← citeshttps://doi.org/10.1145/3377555.3377890openalex-snapshot
Vectorization-aware loop unrolling with seed forwarding
inferred← citeshttps://doi.org/10.1145/3458817.3476149openalex-snapshot
Temporal vectorization for stencils
inferred← citeshttps://doi.org/10.1145/3497776.3517767openalex-snapshot
Loner: utilizing the CPU vector datapath to process scalar integer data
inferred← citeshttps://doi.org/10.1145/3559009.3569663openalex-snapshot
Combining Run-Time Checks and Compile-Time Analysis to Improve Control Flow Auto-Vectorization
inferred← citeshttps://doi.org/10.1145/3582016.3582046openalex-snapshot
Occamy: Elastically Sharing a SIMD Co-processor across Multiple CPU Cores
inferred← citeshttps://doi.org/10.1145/3620666.3651333openalex-snapshot
Boost Linear Algebra Computation Performance via Efficient VNNI Utilization
inferred← citeshttps://doi.org/10.1145/3673038.3673062openalex-snapshot
Optimizing Stencil Computation on Multi-core DSPs
inferred← citeshttps://doi.org/10.1145/3696443.3708917openalex-snapshot
Qiwu: Exploiting Ciphertext-Level SIMD Parallelism in Homomorphic Encryption Programs
inferred← citeshttps://doi.org/10.1145/3710848.3710886openalex-snapshot
Jigsaw: Toward Conflict-free Vectorized Stencil Computation by Tessellating Swizzled Registers
inferred← citeshttps://doi.org/10.1587/transinf.2016edp7236openalex-snapshot
Insufficient Vectorization: A New Method to Exploit Superword Level Parallelism
inferred← citeshttps://doi.org/10.5555/3049832.3049846openalex-snapshot
Automatic generation of fast BLAS3-GEMM: a portable compiler approach
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Super-Node SLP: optimized vectorization for code sequences containing operators and their inverse elements
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