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A Survey on Design Approaches to Circumvent Permanent Faults in Networks-on-Chip
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Outgoing claims: the papers this work cites, builds on, or argues with.
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The Hamiltonian property of generalized de Bruijn digraphs
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The de Bruijn multiprocessor network: a versatile parallel processing and sorting network for VLSI
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Performance Evaluation of Adaptive Routing Algorithms for achieving Fault Tolerance in NoC Fabrics
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Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture
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Fault-Tolerant Routing Algorithm for Network on Chip without Virtual Channels
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Spare sharing network enhancement for scalable systems
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BulletProof: A Defect~Tolerant CMP Switch Architecture
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QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers
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De Bruijn graph based 3D Network on Chip architecture design
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A fine-grained link-level fault-tolerant mechanism for networks-on-chip
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Fault-tolerant routing in A PRDT(2,1)-based NoC
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Reliability of wireless on-chip interconnects based on carbon nanotube antennas
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Reliability in Application Specific Mesh-Based NoC Architectures
inferredcites →https://doi.org/10.1109/ipdps.2000.846045openalex-snapshot
Fault-tolerant wormhole routing algorithms in meshes in the presence of concave faults
inferredcites →https://doi.org/10.1109/ipps.1995.395981openalex-snapshot
A novel deadlock-free routing technique for a class of de Bruijn graph based networks
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Wormhole routing in de Bruijn networks and hyper-de Bruijn networks
inferredcites →https://doi.org/10.1109/iscas.2007.378469openalex-snapshot
Characterization of a Fault-tolerant NoC Router
inferredcites →https://doi.org/10.1109/iscas.2012.6271869openalex-snapshot
Fine-grained splitting methods to address permanent errors in Network-on-Chip links
inferredcites →https://doi.org/10.1109/ispan.1994.367185openalex-snapshot
Message transfer algorithms on the recursive diagonal torus
inferredcites →https://doi.org/10.1109/ispan.1999.778920openalex-snapshot
A torus assignment for an interconnection network recursive diagonal torus
inferredcites →https://doi.org/10.1109/ispan.2005.49openalex-snapshot
Fault-Tolerant Routing Schemes in RDT(2,2,1)/a-Based Interconnection Network for Networks-on-Chip Designs
inferredcites →https://doi.org/10.1109/isqed.2011.5770726openalex-snapshot
A low overhead fault tolerant routing scheme for 3D Networks-on-Chip
inferredcites →https://doi.org/10.1109/isqed.2011.5770788openalex-snapshot
ERAVC: Enhanced reliability aware NoC router
inferredcites →https://doi.org/10.1109/isscc.2008.4523070openalex-snapshot
TILE64 - Processor: A 64-Core SoC with Mesh Interconnect
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5.9 Haswell: A family of IA 22nm processors
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A RDT-based interconnection network for scalable network-on-chip designs
inferredcites →https://doi.org/10.1109/itng.2007.143openalex-snapshot
On the Physicl Layout of PRDT-Based NoCs
inferredcites →https://doi.org/10.1109/itng.2007.195openalex-snapshot
Topology and Binary Routing Schemes of A PRDT-Based NoC
inferredcites →https://doi.org/10.1109/itng.2007.5openalex-snapshot
A Fault tolerant mechanism for handling Permanent and Transient Failures in a Network on Chip
inferredcites →https://doi.org/10.1109/l-ca.2007.16openalex-snapshot
Logic-Based Distributed Routing for NoCs
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Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
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Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance
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Trends and challenges in VLSI circuit reliability
inferredcites →https://doi.org/10.1109/mm.2006.41openalex-snapshot
Synergistic Processing in Cell's Multicore Architecture
inferredcites →https://doi.org/10.1109/mm.2007.4378787openalex-snapshot
Research Challenges for On-Chip Interconnection Networks
inferredcites →https://doi.org/10.1109/nca.2010.14openalex-snapshot
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Implications of Rent's Rule for NoC Design and Its Fault-Tolerance
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A Lightweight Fault-Tolerant Mechanism for Network-on-Chip
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Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing
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A Novel Flit Serialization Strategy to Utilize Partially Faulty Links in Networks-on-Chip
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Transient and Permanent Error Control for High-End Multiprocessor Systems-on-Chip
inferredcites →https://doi.org/10.1109/nocs.2013.6558401openalex-snapshot
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inferredcites →https://doi.org/10.1109/nocs.2014.7008765openalex-snapshot
QuT: A low-power optical Network-on-Chip
inferredcites →https://doi.org/10.1109/pact.2011.61openalex-snapshot
ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment
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High Performance Fault-Tolerant Routing Algorithm for NoC-Based Many-Core Systems
inferredcites →https://doi.org/10.1109/samos.2012.6404161openalex-snapshot
OSR-Lite: Fast and deadlock-free NoC reconfiguration framework
inferredcites →https://doi.org/10.1109/sbac-pad.2013.32openalex-snapshot
Tackling Permanent Faults in the Network-on-Chip Router Pipeline
inferredcites →https://doi.org/10.1109/tc.2003.1183946openalex-snapshot
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Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip
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A Reliable Routing Architecture and Algorithm for NoCs
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A low latency router supporting adaptivity for on-chip interconnects
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A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
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Scalable and fault-tolerant network-on-chip design usingthe quartered recursive diagonal torus topology
inferredcites →https://doi.org/10.1145/1391469.1391584openalex-snapshot
A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip
inferredcites →https://doi.org/10.1145/139669.140384openalex-snapshot
The turn model for adaptive routing
inferredcites →https://doi.org/10.1145/1403375.1403591openalex-snapshot
Defect tolerance in homogeneous manycore processors using core-level redundancy with unified topology
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de Bruijn graph as a low latency scalable architecture for energy efficient massive NoCs
inferredcites →https://doi.org/10.1145/146628.140384openalex-snapshot
The turn model for adaptive routing
inferredcites →https://doi.org/10.1145/1531542.1531658openalex-snapshot
Reliability aware NoC router architecture using input channel buffer sharing
inferredcites →https://doi.org/10.1145/1999946.1999957openalex-snapshot
Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures
inferredcites →https://doi.org/10.1145/1999946.1999965openalex-snapshot
A distributed and topology-agnostic approach for on-line NoC testing
inferredcites →https://doi.org/10.1145/1999946.1999974openalex-snapshot
Complex network inspired fault-tolerant NoC architectures with wireless links
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Low-cost fault-tolerant switch allocator for network-on-chip routers
inferredcites →https://doi.org/10.1145/2155620.2155668openalex-snapshot
Formally enhanced runtime verification to ensure NoC functional correctness
inferredcites →https://doi.org/10.1145/2485984.2485994openalex-snapshot
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs
inferredcites →https://doi.org/10.1145/2522968.2522976openalex-snapshot
Methods for fault tolerance in networks-on-chip
inferredcites →https://doi.org/10.1145/2593069.2593141openalex-snapshot
Fault-tolerant Routing for On-chip Network Without Using Virtual Channels
inferredcites →https://doi.org/10.1145/514191.514204openalex-snapshot
A deterministic fault-tolerant and deadlock-free routing protocol in 2-D meshes based on odd-even turn model
inferredcites →https://doi.org/10.1155/2007/94676openalex-snapshot
Online Reconfigurable Self-Timed Links for Fault Tolerant NoC
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Designing Network On-Chip Architectures in the Nanoscale Era
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A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
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A highly resilient routing algorithm for fault-tolerant NoCs
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On the design and analysis of fault tolerant NoC architecture using spare routers
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A resilient on-chip router design through data path salvaging
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AFRA: a low cost high performance reliable routing for 3D mesh NoCs
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Brisk and limited-impact NoC routing reconfiguration
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d 2 -LBDR: Distance-driven routing to handle permanent failures in 2D mesh NoCs
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Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Fault-Tolerant Mesh-Based NoC with Router-Level Redundancy
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Multi-objective biogeography-based optimization and reinforcement learning hybridization for network-on chip reliability improvement
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Abacus turn model-based routing for NoC interconnects with switch or link failures
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An improved reconfiguration algorithm for handling 1-point NoC failures
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HDL Environment for the Synthesis of 2-Dimensional and 3- Dimensional Network on Chip Mesh Router Architecture
inferred← citeshttps://doi.org/10.1109/iccd50377.2020.00046openalex-snapshot
Multiple Permanent Faults Mitigation Through Bit-Shuffling for Network-on-Chip Architecture
inferred← citeshttps://doi.org/10.1109/iolts.2017.8046172openalex-snapshot
Deterministic network on chip for deploying real time applications on many-core processors
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Investigating Reliability and Security of Integrated Circuits and Systems
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Methodology for Formal Verification of Hardware Safety Strategies Using SMT
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Online reconfigurable routing method for handling link failures in NoC-based MPSoCs
inferred← citeshttps://doi.org/10.1109/tcad.2021.3101406openalex-snapshot
BiSuT: A NoC-Based Bit-Shuffling Technique for Multiple Permanent Faults Mitigation
inferred← citeshttps://doi.org/10.1109/tvlsi.2017.2729081openalex-snapshot
Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/tvlsi.2018.2803478openalex-snapshot
Reliability-Aware Test Methodology for Detecting Short-Channel Faults in On-Chip Networks
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Providing Integrity in Real-Time Networks-on-Chip
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Performance-Aware Test Scheduling for Diagnosing Coexistent Channel Faults in Topology-Agnostic Networks-on-Chip
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Design analysis of moth-flame optimized fault tolerant technique for minimally buffered network-on-chip router
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A Survey on Fault-Tolerant Methodologies for Deep Neural Networks
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Collaborative Routing Algorithm for Fault Tolerance in Network on Chip CRAFT NoC
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Fault tolerant and congestion aware routing algorithm for network on chip1
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A new architecture for online error detection and isolation in network on chip
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RescueSNN: enabling reliable executions on spiking neural network accelerators under permanent faults
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NoCGuard: A Reliable Network-on-Chip Router Architecture
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Topology Reconfiguration for NoCs: A Fast Reconfiguration Algorithm Based on Monotonic Path Shifting
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Reliability and Security Challenges in Electrical/Optical On-Chip Interconnects for IoT Applications
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A New Fault Tolerant Routing Algorithm for Networks on Chip
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Runtime Mitigation of Packet Drop Attacks in Fault-tolerant Networks-on-Chip
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