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Designing Network On-Chip Architectures in the Nanoscale Era

https://doi.org/10.1201/b10477
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Fault Localization in NoCs Exploiting Periodic Heartbeat Messages in a Many-Core Environment
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Reconfigurable Optical Wireless Switches for On-Chip Interconnection
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Fault-Tolerant Vertical Link Design for Effective 3D Stacking
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NoC Reconfiguration for CMP Virtualization
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Transient and Permanent Error Control for High-End Multiprocessor Systems-on-Chip
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Exploring NoC Virtualization Alternatives in CMPs
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The Need for 2-Phase Design Paradigms in High-Throughput GALS Network-On-Chip Architectures
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Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems
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Merged Switch Allocation and Traversal in Network-on-Chip Switches
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An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication
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A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms
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On All-to-All Broadcast in Dense Gaussian Network On-Chip
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All-To-All Broadcast in Hexagonal Torus Networks On-Chip
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Efficient routing implementation in complex systems-on-chip designs
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Heterogeneous network design for effective support of invalidation-based coherency protocols
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Physical-aware system-level design for tiled hierarchical chip multiprocessors
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Designing best effort networks-on-chip to meet hard latency constraints
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A feature-rich NoC switch with cross-feature optimizations for the next generation of reliable and reconfigurable embedded systems
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A Survey on Design Approaches to Circumvent Permanent Faults in Networks-on-Chip
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Design technology for fault-free and maximally-parallel wavelength-routed optical networks-on-chip
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Machine Learning Enabled Solutions for Design and Optimization Challenges in Networks-on-Chip based Multi/Many-Core Architectures
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COUNTERREENGINEERING OF ELECTRONIC DEVICES
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Improving Network-on-Chip Performance in Multi-Core Systems
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Design Space Exploration for Networks On-chip
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Integrated Architecture for Configuration and Service Management in MANET Environments
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Addressing Manufacturing Challenges in NoC-based ULSI Designs
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Floorplan-Aware High Performance NoC Design
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High Performance and Power Efficient On-Chip Network Designs through Multiple Injection Ports
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Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors
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Head-of-Line Blocking Reduction in Power-Efficient Networks-on-Chip
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Guided Participatory Research on Parallel Computer Architectures for K-12 Students Through a Narrative Approach
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Contribution to the architecture and implementation of Bi-NoC routers for multi-synchronous GALS systems
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Probabilistically time-analyzable complex processor designs
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A time-predictable many-core processor design for critical real-time embedded systems
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Practical strategies to monitor and control contention in shared resources of critical real-time embedded systems
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Automatic synthesis and optimization of chip multiprocessors
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Actas de simposio-taller Estrategias y herramientas para el aprendizaje y la evaluación (Jenui 2013)
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