On the public citation graph

A Software Cache Partitioning System for Hash-Based Caches

0 signed · 56 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/s10766-014-0334-5openalex-snapshot
A Phase Behavior Aware Dynamic Cache Partitioning Scheme for CMPs
inferredcites →https://doi.org/10.1109/aeect.2013.6716445openalex-snapshot
SCIP: Selective cache insertion and bypassing to improve the performance of last-level caches
inferredcites →https://doi.org/10.1109/aeect34041.2015openalex-snapshot
2015 IEEE Jordan Conference on Applied Electrical Engineering and Computing Technologies (AEECT)
inferredcites →https://doi.org/10.1109/dsd.2015.56openalex-snapshot
Systematic Reverse Engineering of Cache Slice Selection in Intel Processors
inferredcites →https://doi.org/10.1109/ecrts.2013.19openalex-snapshot
A Coordinated Approach for Practical OS-Level Cache Management in Multi-core Real-Time Systems
inferredcites →https://doi.org/10.1109/hotchips.2011.7477509openalex-snapshot
2nd Generation Intel® Core Processor Family: Intel® Core i7, i5 and i3
inferredcites →https://doi.org/10.1109/hpca.2008.4658653openalex-snapshot
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems
inferredcites →https://doi.org/10.1109/hpca.2013.6522315openalex-snapshot
Modeling performance variation due to cache sharing
inferredcites →https://doi.org/10.1109/hpca.2014.6835954openalex-snapshot
Improving cache performance using read-write partitioning
inferredcites →https://doi.org/10.1109/hpca32246.2014openalex-snapshot
2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
inferredcites →https://doi.org/10.1109/icpp.2015.24openalex-snapshot
Spatial Locality-Aware Cache Partitioning for Effective Cache Sharing
inferredcites →https://doi.org/10.1109/icpp.2015.84openalex-snapshot
Optimal Cache Partition-Sharing
inferredcites →https://doi.org/10.1109/ispa.2009.47openalex-snapshot
A Simple Cache Partitioning Approach in a Virtualized Environment
inferredcites →https://doi.org/10.1109/micro.2006.49openalex-snapshot
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches
inferredcites →https://doi.org/10.1109/micro.2008.4771796openalex-snapshot
Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer
inferredcites →https://doi.org/10.1109/micro.2010.20openalex-snapshot
The ZCache: Decoupling Ways and Associativity
inferredcites →https://doi.org/10.1109/micro.2014.46openalex-snapshot
Futility Scaling: High-Associativity Cache Partitioning
inferredcites →https://doi.org/10.1109/sp.2013.23openalex-snapshot
Practical Timing Side Channel Attacks against Kernel Space ASLR
inferredcites →https://doi.org/10.1109/tc.2015.2462813openalex-snapshot
Rethinking Memory Management in Modern Operating System: Horizontal, Vertical or Random?
inferredcites →https://doi.org/10.1109/trustcom.2012.25openalex-snapshot
A Dynamic Cache Partitioning Mechanism under Virtualization Environment
inferredcites →https://doi.org/10.1145/1186736.1186737openalex-snapshot
SPEC CPU2006 benchmark descriptions
inferredcites →https://doi.org/10.1145/1250662.1250709openalex-snapshot
Adaptive insertion policies for high performance caching
inferredcites →https://doi.org/10.1145/1454115.1454128openalex-snapshot
The PARSEC benchmark suite
inferredcites →https://doi.org/10.1145/1519065.1519076openalex-snapshot
Towards practical page coloring-based multicore cache management
inferredcites →https://doi.org/10.1145/1646353.1646371openalex-snapshot
Managing contention for shared resources on multicore processors
inferredcites →https://doi.org/10.1145/1815961.1815971openalex-snapshot
High performance cache replacement using re-reference interval prediction (RRIP)
inferredcites →https://doi.org/10.1145/1966445.1966468openalex-snapshot
SRM-buffer
inferredcites →https://doi.org/10.1145/2000064.2000073openalex-snapshot
Vantage
inferredcites →https://doi.org/10.1145/2155620.2155650openalex-snapshot
Bubble-Up
inferredcites →https://doi.org/10.1145/2228360.2228482openalex-snapshot
Courteous cache sharing
inferredcites →https://doi.org/10.1145/2370816.2370862openalex-snapshot
Optimal bypass monitor for high performance last-level caches
inferredcites →https://doi.org/10.1145/2370816.2370868openalex-snapshot
The evicted-address filter
inferredcites →https://doi.org/10.1145/2485922.2485949openalex-snapshot
A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness
inferredcites →https://doi.org/10.1145/2485922.2485974openalex-snapshot
Bubble-flux
inferredcites →https://doi.org/10.1145/2499368.2451125openalex-snapshot
Paragon
inferredcites →https://doi.org/10.1145/2508148.2485974openalex-snapshot
Bubble-flux
inferredcites →https://doi.org/10.1145/2628071.2628104openalex-snapshot
COLORIS
inferredcites →https://doi.org/10.1145/365628.365655openalex-snapshot
A fast storage allocator

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/s11241-020-09351-2openalex-snapshot
Supporting I/O and IPC via fine-grained OS isolation for mixed-criticality real-time tasks
inferred← citeshttps://doi.org/10.1016/j.sysarc.2018.12.007openalex-snapshot
Locality-aware cache random replacement policies
inferred← citeshttps://doi.org/10.1109/access.2021.3058280openalex-snapshot
Optimizing Coherence Traffic in Manycore Processors Using Closed-Form Caching/Home Agent Mappings
inferred← citeshttps://doi.org/10.1109/access.2022.3151891openalex-snapshot
A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms
inferred← citeshttps://doi.org/10.1109/jsac.2023.3339749openalex-snapshot
AIRIC: Orchestration of Virtualized Radio Access Networks With Noisy Neighbours
inferred← citeshttps://doi.org/10.1109/pact.2017.19openalex-snapshot
Application Clustering Policies to Address System Fairness with Intel’s Cache Allocation Technology
inferred← citeshttps://doi.org/10.1109/tc.2020.2968066openalex-snapshot
Page Reusability-Based Cache Partitioning for Multi-Core Systems
inferred← citeshttps://doi.org/10.1109/tc.2021.3112970openalex-snapshot
LFOC+: A Fair OS-level Cache-Clustering Policy for Commodity Multicore Systems
inferred← citeshttps://doi.org/10.1145/3273905.3273911openalex-snapshot
Supporting I/O and IPC via Fine-Grained OS Isolation for Mixed-Criticality Real-Time Tasks
inferred← citeshttps://doi.org/10.1145/3297280.3297423openalex-snapshot
Cache-aware block allocation for memory-technology storage targeted file systems
inferred← citeshttps://doi.org/10.1145/3302424.3303977openalex-snapshot
Make the Most out of Last Level Cache in Intel Processors
inferred← citeshttps://doi.org/10.1145/3337821.3337925openalex-snapshot
LFOC
inferred← citeshttps://doi.org/10.1145/3472883.3487006openalex-snapshot
Provisioning Differentiated Last-Level Cache Allocations to VMs in Public Clouds
inferred← citeshttps://doi.org/10.1145/3710848.3710863openalex-snapshot
SGDRC: Software-Defined Dynamic Resource Control for Concurrent DNN Inference on NVIDIA GPUs
inferred← citeshttps://doi.org/10.1145/3774934.3786415openalex-snapshot
Cacheman: A Comprehensive Last-Level Cache Management System for Multi-tenant Clouds
inferred← citeshttps://doi.org/10.23919/date69613.2026.11539654openalex-snapshot
Colored Huge Pages: A Hardware-Software Approach for Enhanced Isolation and Performance
inferred← citeshttps://doi.org/10.4995/thesis/10251/112423openalex-snapshot
Adaptive Prefetching and Cache Partitioning for Multicore Processors
inferred← citeshttps://doi.org/10.5821/dissertation-2117-366909openalex-snapshot
Smart hardware designs for probabilistically-analyzable processor architectures
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.