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Recent Attacks and Defenses on FPGA-based Systems
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11894063_25openalex-snapshot
Offline Hardware/Software Authentication for Reconfigurable Platforms
inferredcites →https://doi.org/10.1007/3-540-49380-8_2openalex-snapshot
Fingerprinting Digital Circuits on Programmable Hardware
inferredcites →https://doi.org/10.1007/978-1-4419-8080-9openalex-snapshot
Introduction to Hardware Security and Trust
inferredcites →https://doi.org/10.1007/978-1-4614-7915-4_9openalex-snapshot
A Survey of Recent Results in FPGA Security and Intellectual Property Protection
inferredcites →https://doi.org/10.1007/978-3-540-74735-2_5openalex-snapshot
FPGA Intrinsic PUFs and Their Use for IP Protection
inferredcites →https://doi.org/10.1007/978-3-540-89598-5_18openalex-snapshot
Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems
inferredcites →https://doi.org/10.1007/978-3-642-00641-8_8openalex-snapshot
A Protocol for Secure Remote Updates of FPGA Configurations
inferredcites →https://doi.org/10.1007/978-3-642-33027-8_2openalex-snapshot
Breakthrough Silicon Scanning Discovers Backdoor in Military Chip
inferredcites →https://doi.org/10.1007/978-3-642-40349-1_1openalex-snapshot
On the Simplicity of Converting Leakages from Multivariate to Univariate
inferredcites →https://doi.org/10.1007/978-94-007-1338-3openalex-snapshot
Security Trends for FPGAS: From Secured to Secure Reconfigurable Systems
inferredcites →https://doi.org/10.1007/s11265-007-0136-8openalex-snapshot
Power Signature Watermarking of IP Cores for FPGAs
inferredcites →https://doi.org/10.1007/s11390-014-1458-1openalex-snapshot
A Survey on Silicon PUFs and Recent Advances in Ring Oscillator PUFs
inferredcites →https://doi.org/10.1016/j.vlsi.2016.01.004openalex-snapshot
A survey of hardware Trojan threat and defense
inferredcites →https://doi.org/10.1108/ir.1999.04926fae.001openalex-snapshot
Lecture Notes in Computer Science 1205
inferredcites →https://doi.org/10.1109/43.952740openalex-snapshot
Constraint-based watermarking techniques for design IP protection
inferredcites →https://doi.org/10.1109/43.952741openalex-snapshot
Fingerprinting techniques for field-programmable gate array intellectual property protection
inferredcites →https://doi.org/10.1109/access.2018.2844548openalex-snapshot
T2FA: Transparent Two-Factor Authentication
inferredcites →https://doi.org/10.1109/cloud.2014.46openalex-snapshot
PFC: Privacy Preserving FPGA Cloud - A Case Study of MapReduce
inferredcites →https://doi.org/10.1109/dft.2013.6653606openalex-snapshot
Secure Split-Test for preventing IC piracy by untrusted foundry and assembly
inferredcites →https://doi.org/10.1109/fccm.2015.55openalex-snapshot
Protecting against Cryptographic Trojans in FPGAs
inferredcites →https://doi.org/10.1109/fccm.2018.00016openalex-snapshot
FPGA Side Channel Attacks without Physical Access
inferredcites →https://doi.org/10.1109/fdtc.2008.11openalex-snapshot
A Generic Fault Countermeasure Providing Data and Program Flow Integrity
inferredcites →https://doi.org/10.1109/fdtc.2010.14openalex-snapshot
Multi Fault Laser Attacks on Protected CRT-RSA
inferredcites →https://doi.org/10.1109/fpl.2008.4629951openalex-snapshot
Secure FPGA configuration architecture preventing system downgrade
inferredcites →https://doi.org/10.1109/fpl.2009.5272250openalex-snapshot
IP protection in Partially Reconfigurable FPGAs
inferredcites →https://doi.org/10.1109/fpl.2010.44openalex-snapshot
Secure Protocol Implementation for Remote Bitstream Update Preventing Replay Attacks on FPGA
inferredcites →https://doi.org/10.1109/fpl.2012.6339241openalex-snapshot
SecURe DPR: Secure update preventing replay attacks for dynamic partial reconfiguration
inferredcites →https://doi.org/10.1109/fpl.2012.6339242openalex-snapshot
FPGAs for trusted cloud computing
inferredcites →https://doi.org/10.1109/fpt.2006.270368openalex-snapshot
Proceedings 2006 IEEE International Conference on Field Programmable Technology
inferredcites →https://doi.org/10.1109/fpt.2007.4439216openalex-snapshot
Proceedings 2007 International Conference on Field Programmable Technology
inferredcites →https://doi.org/10.1109/fpt.2007.4439246openalex-snapshot
Dynamic Intellectual Property Protection for Reconfigurable Devices
inferredcites →https://doi.org/10.1109/fpt.2008.4762385openalex-snapshot
Netlist-level IP protection by watermarking for LUT-based FPGAs
inferredcites →https://doi.org/10.1109/fpt.2014.7082768openalex-snapshot
A survey on security and trust of FPGA-based systems
inferredcites →https://doi.org/10.1109/hldvt.2009.5340158openalex-snapshot
Hardware Trojan: Threats and emerging solutions
inferredcites →https://doi.org/10.1109/host54066.2022.9839913openalex-snapshot
Proceedings of the 2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)
inferredcites →https://doi.org/10.1109/hst.2012.6224325openalex-snapshot
Reverse engineering circuits using behavioral pattern mining
inferredcites →https://doi.org/10.1109/hst.2014.6855560openalex-snapshot
Split-fabrication obfuscation: Metrics and techniques
inferredcites →https://doi.org/10.1109/hst.2018.8383907openalex-snapshot
FPGA-oriented moving target defense against security threats from malicious FPGA tools
inferredcites →https://doi.org/10.1109/icccn.2018.8487347openalex-snapshot
A Fully Digital Physical Unclonable Function Based Temperature Sensor for Secure Remote Sensing
inferredcites →https://doi.org/10.1109/iolts.2017.8046200openalex-snapshot
VPUF: Voter based physical unclonable function with high reliability and modeling attack resistance
inferredcites →https://doi.org/10.1109/isqed.2018.8357320openalex-snapshot
Securing FPGA-based obsolete component replacement for legacy systems
inferredcites →https://doi.org/10.1109/isvlsi.2012.40openalex-snapshot
Nano-PPUF: A Memristor-Based Security Primitive
inferredcites →https://doi.org/10.1109/jiot.2018.2866164openalex-snapshot
HCIC: Hardware-Assisted Control-Flow Integrity Checking
inferredcites →https://doi.org/10.1109/jproc.2014.2320516openalex-snapshot
Physical Unclonable Functions and Applications: A Tutorial
inferredcites →https://doi.org/10.1109/mdt.2008.166openalex-snapshot
Managing Security in FPGA-Based Embedded Systems
inferredcites →https://doi.org/10.1109/mdt.2010.7openalex-snapshot
A Survey of Hardware Trojan Taxonomy and Detection
inferredcites →https://doi.org/10.1109/mdt.2012.2196252openalex-snapshot
Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution
inferredcites →https://doi.org/10.1109/mdt.2013.2247460openalex-snapshot
Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream
inferredcites →https://doi.org/10.1109/mspec.2008.4505310openalex-snapshot
The Hunt For The Kill Switch
inferredcites →https://doi.org/10.1109/reconfig.2012.6416743openalex-snapshot
Efficient and side-channel resistant authenticated encryption of FPGA bitstreams
inferredcites →https://doi.org/10.1109/recosoc.2015.7238102openalex-snapshot
A survey on security features in modern FPGAs
inferredcites →https://doi.org/10.1109/secpri.2004.1301305openalex-snapshot
Proceedings 2004 IEEE Symposium on Security and Privacy
inferredcites →https://doi.org/10.1109/sp.2018.00049openalex-snapshot
FPGA-Based Remote Power Side-Channel Attacks
inferredcites →https://doi.org/10.1109/tc.2006.135openalex-snapshot
An RSA Implementation Resistant to Fault Attacks and to Simple Power Analysis
inferredcites →https://doi.org/10.1109/tc.2008.212openalex-snapshot
Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers
inferredcites →https://doi.org/10.1109/tcad.2002.804205openalex-snapshot
Publicly detectable watermarking for intellectual property authentication in VLSI design
inferredcites →https://doi.org/10.1109/tcad.2002.804378openalex-snapshot
Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers
inferredcites →https://doi.org/10.1109/tcad.2016.2638445openalex-snapshot
PUF-Based Fuzzy Authentication Without Error Correcting Codes
inferredcites →https://doi.org/10.1109/tcad.2017.2729340openalex-snapshot
DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures
inferredcites →https://doi.org/10.1109/tcad.2017.2740296openalex-snapshot
SD-PUF: Spliced Digital Physical Unclonable Function
inferredcites →https://doi.org/10.1109/tcsi.2018.2855061openalex-snapshot
A Low Power Diode-Clamped Inverter-Based Strong Physical Unclonable Function for Robust and Lightweight Authentication
inferredcites →https://doi.org/10.1109/test.2004.1387397openalex-snapshot
Low cost concurrent error detection for the advanced encryption standard
inferredcites →https://doi.org/10.1109/tie.2019.2938462openalex-snapshot
Physical Unclonable Function-Based Key Sharing via Machine Learning for IoT Security
inferredcites →https://doi.org/10.1109/tifs.2011.2163307openalex-snapshot
Provably Secure Active IC Metering Techniques for Piracy Avoidance and Digital Rights Management
inferredcites →https://doi.org/10.1109/tifs.2011.2169667openalex-snapshot
A Pay-per-Use Licensing Scheme for Hardware IP Cores in Recent SRAM-Based FPGAs
inferredcites →https://doi.org/10.1109/tifs.2015.2400413openalex-snapshot
A PUF-FSM Binding Scheme for FPGA IP Protection and Pay-Per-Device Licensing
inferredcites →https://doi.org/10.1109/tifs.2017.2738600openalex-snapshot
Key-Based Dynamic Functional Obfuscation of Integrated Circuits Using Sequentially Triggered Mode-Based Design
inferredcites →https://doi.org/10.1109/tii.2010.2068303openalex-snapshot
A Flexible Design Flow for Software IP Binding in FPGA
inferredcites →https://doi.org/10.1109/tmscs.2018.2877737openalex-snapshot
Frequency Offset-Based Ring Oscillator Physical Unclonable Function
inferredcites →https://doi.org/10.1109/tvlsi.2005.859470openalex-snapshot
Extracting secret keys from integrated circuits
inferredcites →https://doi.org/10.1109/tvlsi.2011.2162347openalex-snapshot
Secure Public Verification of IP Marks in FPGA Design Through a Zero-Knowledge Protocol
inferredcites →https://doi.org/10.1109/tvlsi.2015.2437996openalex-snapshot
A Practical Logic Obfuscation Technique for Hardware Security
inferredcites →https://doi.org/10.1109/tvlsi.2016.2619682openalex-snapshot
Publicly Verifiable Watermarking for Intellectual Property Protection in FPGA Design
inferredcites →https://doi.org/10.1109/vlsi.design.2010.54openalex-snapshot
RTL Hardware IP Protection Using Key-Based Control and Data Flow Obfuscation
inferredcites →https://doi.org/10.1109/vts.2013.6548925openalex-snapshot
A multi-faceted approach to FPGA-based Trojan circuit detection
inferredcites →https://doi.org/10.1145/1233501openalex-snapshot
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design - ICCAD '06
inferredcites →https://doi.org/10.1145/1278480.1278484openalex-snapshot
Physical unclonable functions for device authentication and secret key generation
inferredcites →https://doi.org/10.1145/1344671.1344729openalex-snapshot
From the bitstream to the netlist
inferredcites →https://doi.org/10.1145/1450095.1450129openalex-snapshot
Active control and digital rights management of integrated circuit IP cores
inferredcites →https://doi.org/10.1145/1629911.1630093openalex-snapshot
Information hiding for trusted system design
inferredcites →https://doi.org/10.1145/1950413.1950432openalex-snapshot
Authenticated encryption for FPGA bitstreams
inferredcites →https://doi.org/10.1145/2024724.2024805openalex-snapshot
The state-of-the-art in semiconductor reverse engineering
inferredcites →https://doi.org/10.1145/2046707.2046722openalex-snapshot
On the vulnerability of FPGA bitstream encryption against power analysis attacks
inferredcites →https://doi.org/10.1145/2435264.2435282openalex-snapshot
Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II
inferredcites →https://doi.org/10.1145/2508859.2516656openalex-snapshot
Security analysis of integrated circuit camouflaging
inferredcites →https://doi.org/10.1145/2591513.2591520openalex-snapshot
Hardware trojan attacks in FPGA devices
inferredcites →https://doi.org/10.1145/2699833openalex-snapshot
Reconfigurable Binding against FPGA Replay Attacks
inferredcites →https://doi.org/10.1145/2755563openalex-snapshot
A Survey on Chip to System Reverse Engineering
inferredcites →https://doi.org/10.1145/277044.277240openalex-snapshot
Watermarking techniques for intellectual property protection
inferredcites →https://doi.org/10.1145/2816818openalex-snapshot
Emerging Technology-Based Design of Primitives for Hardware Security
inferredcites →https://doi.org/10.1145/2816822openalex-snapshot
Compact and On-the-Fly Secure Dynamic Reconfiguration for Volatile FPGAs
inferredcites →https://doi.org/10.1145/288548.288606openalex-snapshot
Signature hiding techniques for FPGA intellectual property protection
inferredcites →https://doi.org/10.1145/2897937.2898061openalex-snapshot
Physical unclonable functions-based linear encryption against code reuse attacks
inferredcites →https://doi.org/10.1145/309847.310080openalex-snapshot
Robust FPGA intellectual property protection through multiple small watermarks
inferredcites →https://doi.org/10.1145/3240765.3240841openalex-snapshot
Remote inter-chip power analysis side-channel attacks at board-level
inferredcites →https://doi.org/10.1145/337292.337586openalex-snapshot
Fingerprinting intellectual property using constraint-addition
inferredcites →https://doi.org/10.1145/503048.503065openalex-snapshot
Cryptographic rights management of FPGA intellectual property cores
inferredcites →https://doi.org/10.1145/764808.764847openalex-snapshot
Zero overhead watermarking technique for FPGA designs
inferredcites →https://doi.org/10.1561/1000000005openalex-snapshot
FPGA Architecture: Survey and Challenges
inferredcites →https://doi.org/10.1561/9781601981271openalex-snapshot
FPGA Architecture: Survey and Challenges
inferredcites →https://doi.org/10.1587/elex.9.1735openalex-snapshot
Efficient verification of IP watermarks in FPGA designs through lookup table content extracting
inferredcites →https://doi.org/10.23919/fpl.2017.8056840openalex-snapshot
Voltage drop-based fault attacks on FPGAs using valid bitstreams
inferredcites →https://doi.org/10.5555/1326073.1326215openalex-snapshot
Remote activation of ICs for piracy prevention and digital right management
inferredcites →https://doi.org/10.5555/2485288.2485594openalex-snapshot
Reverse engineering digital circuits using functional analysis
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-031-16344-9_14openalex-snapshot
FPGA Security: Security Threats from Untrusted FPGA CAD Toolchain
inferred← citeshttps://doi.org/10.1007/978-3-031-45395-3_6openalex-snapshot
Contention-Based Threats Between Single-Tenant Cloud FPGA Instances
inferred← citeshttps://doi.org/10.1007/978-3-031-46077-7_25openalex-snapshot
Towards Privacy-First Security Enablers for 6G Networks: The PRIVATEER Approach
inferred← citeshttps://doi.org/10.1007/978-3-031-55673-9_11openalex-snapshot
Secure eFPGA Configuration: A System-Level Approach
inferred← citeshttps://doi.org/10.1007/978-3-031-55673-9_17openalex-snapshot
Trusted Computing Architectures for IoT Devices
inferred← citeshttps://doi.org/10.1007/s11042-022-12451-9openalex-snapshot
On FPGA implementation in medical secret image sharing with data hiding
inferred← citeshttps://doi.org/10.1007/s11227-024-06538-3openalex-snapshot
Self-aware decentralized security for real time approximate computing tasks in FPGA-based edge platforms
inferred← citeshttps://doi.org/10.1007/s13369-024-09562-wopenalex-snapshot
A Systematic Literature Review on Vulnerabilities, Mitigation Techniques, and Attacks in Field-Programmable Gate Arrays
inferred← citeshttps://doi.org/10.1007/s41635-021-00122-4openalex-snapshot
Turning the Table: Using Bitstream Reverse Engineering to Detect FPGA Trojans
inferred← citeshttps://doi.org/10.1007/s41635-021-00123-3openalex-snapshot
A Secure Boot Framework with Multi-security Features and Logic-Locking Applications for Reconfigurable Logic
inferred← citeshttps://doi.org/10.1016/j.cose.2026.105119openalex-snapshot
A reverse-engineering toolchain for Microsemi flash-based FPGAs
inferred← citeshttps://doi.org/10.1016/j.jisa.2021.102861openalex-snapshot
Attacks on cryptosystems implemented via VLSI: A review
inferred← citeshttps://doi.org/10.1016/j.micpro.2020.103180openalex-snapshot
Efficient and Lightweight FPGA-based Hybrid PUFs with Improved Performance
inferred← citeshttps://doi.org/10.1016/j.micpro.2025.105186openalex-snapshot
Access control and security analysis of shared accelerators with hardware-level scheduling
inferred← citeshttps://doi.org/10.1016/j.microrel.2025.115941openalex-snapshot
A temperature-invariant and ML-resilient, RO PUF design with improved security and performance metrics
inferred← citeshttps://doi.org/10.1016/j.sysarc.2022.102543openalex-snapshot
Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer
inferred← citeshttps://doi.org/10.1016/j.vlsi.2021.06.001openalex-snapshot
FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures
inferred← citeshttps://doi.org/10.1080/02564602.2022.2158952openalex-snapshot
Reliability Issues in State-of-the-Art Microfluidic Biochips: A Survey
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FPGA-based Design of Multiple Models for Industry 4.0 Cyber Security
inferred← citeshttps://doi.org/10.1093/cybsec/tyac009openalex-snapshot
Drivers and barriers for secure hardware adoption across ecosystem stakeholders
inferred← citeshttps://doi.org/10.1109/access.2020.2965016openalex-snapshot
A Survey on Machine Learning Against Hardware Trojan Attacks: Recent Advances and Challenges
inferred← citeshttps://doi.org/10.1109/access.2020.3023255openalex-snapshot
FPGA-Based Hardware Accelerator for Leveled Ring-LWE Fully Homomorphic Encryption
inferred← citeshttps://doi.org/10.1109/access.2021.3100618openalex-snapshot
UCloD: Small Clock Delays to Mitigate Remote Power Analysis Attacks
inferred← citeshttps://doi.org/10.1109/access.2021.3124565openalex-snapshot
A Cyber Security Evaluation Framework for In-Vehicle Electrical Control Units
inferred← citeshttps://doi.org/10.1109/access.2022.3151430openalex-snapshot
Design and Implementation of Secure Cryptographic System on Chip for Internet of Things
inferred← citeshttps://doi.org/10.1109/access.2022.3173287openalex-snapshot
A Survey on Hardware Vulnerability Analysis Using Machine Learning
inferred← citeshttps://doi.org/10.1109/access.2023.3300222openalex-snapshot
Contact-Less Integrity Verification of Microelectronics Using Near-Field EM Analysis
inferred← citeshttps://doi.org/10.1109/access.2023.3331507openalex-snapshot
FPGA Bitstream Modification: Attacks and Countermeasures
inferred← citeshttps://doi.org/10.1109/access.2024.3351354openalex-snapshot
Diversified Intelligent Terminal Devices Unified Access and Data Communication Technology
inferred← citeshttps://doi.org/10.1109/access.2024.3400624openalex-snapshot
Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories
inferred← citeshttps://doi.org/10.1109/admit67050.2025.11336831openalex-snapshot
Incremental Compilation-Based Clock Margin Optimization for FPGA
inferred← citeshttps://doi.org/10.1109/candarw51189.2020.00033openalex-snapshot
Netlist-based Measures for Hardware Obfuscation: A Preliminary Study
inferred← citeshttps://doi.org/10.1109/dsd64264.2024.00044openalex-snapshot
Hardware-level Access Control and Scheduling of Shared Hardware Accelerators
inferred← citeshttps://doi.org/10.1109/host54066.2022.9839731openalex-snapshot
Security Threats and Countermeasure Deployment Using Partial Reconfiguration in FPGA CAD Tools
inferred← citeshttps://doi.org/10.1109/iccd65941.2025.00080openalex-snapshot
ECOLogic: Enabling Circular, Obfuscated, and Adaptive Logic via eFPGA-Augmented SoCs
inferred← citeshttps://doi.org/10.1109/icces51350.2021.9489054openalex-snapshot
A Counter Measure to Prevent Timing-based Side-Channel Attack on FPGA
inferred← citeshttps://doi.org/10.1109/icces57224.2023.10192646openalex-snapshot
FPGA based Fault Analysis for Encrypted Code
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Security Acceptance Criteria for FPGA Device Adoption in Nuclear Safety-Critical Systems
inferred← citeshttps://doi.org/10.1109/iemcon56893.2022.9946490openalex-snapshot
Memory Isolation for Multi-Tenant Data Integrity in Cloud MPSoC FPGAs
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Research on the Security of SRAM base FPGAs in the Era of Artificial Intelligence
inferred← citeshttps://doi.org/10.1109/iscas56072.2025.11043179openalex-snapshot
Long-Short-GNN: A Novel Graph Neural Network for Detecting FPGA IP Circuits for Hardware Assurance
inferred← citeshttps://doi.org/10.1109/iscas58744.2024.10558465openalex-snapshot
REVBiT: REVerse Engineering of BiTstream for LUT Extraction & Logic Identification
inferred← citeshttps://doi.org/10.1109/isvlsi51109.2021.00058openalex-snapshot
New Security Threats on FPGAs: From FPGA Design Tools Perspective
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TiAS: Time Aware Split Computing to Secure AI/ML Workloads for FPGA based Edge Platforms against Unintentional Delays
inferred← citeshttps://doi.org/10.1109/isvlsi65124.2025.11130215openalex-snapshot
PRIVATEER: Secure FPGA Acceleration for 6G AI Edge Analytics
inferred← citeshttps://doi.org/10.1109/itc-asia.2019.00020openalex-snapshot
Implementation of Parametric Hardware Trojan in FPGA
inferred← citeshttps://doi.org/10.1109/jiot.2020.2974281openalex-snapshot
Deep Reinforcement Learning for Resource Protection and Real-Time Detection in IoT Environment
inferred← citeshttps://doi.org/10.1109/mdat.2022.3142199openalex-snapshot
Long-Wire Leakage: The Threat of Crosstalk
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A Survey on Security Threats and Countermeasures in FPGA-Based Robotic Computing Systems
inferred← citeshttps://doi.org/10.1109/mwscas57524.2023.10405953openalex-snapshot
Ring Oscillator PUF and Blockchain: A Way of Securing Post Fabrication FPGA Supply Chain
inferred← citeshttps://doi.org/10.1109/naecon70028.2026.11675719openalex-snapshot
CRYPTIC: CRYptographic FPGA Targeting through Intelligent Corruption
inferred← citeshttps://doi.org/10.1109/paine54418.2021.9707700openalex-snapshot
Bitstream Reverse Engineering of Microsemi’s VersaTile-based FPGAs
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Isolation Forest Based TinyML for Detecting Hardware Trojans on FPGA in Real Time
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On How FPGAs are Changing the Computer Security Panorama: An Educational Survey
inferred← citeshttps://doi.org/10.1109/smc-it64853.2025.00011openalex-snapshot
Cybershield: Secure Boot for Obfuscated Instruction Codes
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C 3 APSULe: Cross-FPGA Covert-Channel Attacks through Power Supply Unit Leakage
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GraphClusNet: A Hierarchical Graph Neural Network for Recovered Circuit Netlist Partitioning
inferred← citeshttps://doi.org/10.1109/tc.2021.3095657openalex-snapshot
STT-MRAM-Based Reliable Weak PUF
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Toward Building and Optimizing Trustworthy Systems Using Untrusted Components: A Graph-Theoretic Perspective
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Adversarial Hardware With Functional and Topological Camouflage
inferred← citeshttps://doi.org/10.1109/tdsc.2025.3568217openalex-snapshot
Trojan Detection in Digital Microfluidic Biochips via Image Classification: A Deep-Learning Based Approach
inferred← citeshttps://doi.org/10.1109/ticps.2025.3649161openalex-snapshot
Alexis: Anomaly-Based Intrusion Detection in FPGA-Enabled Cyber-Physical Systems
inferred← citeshttps://doi.org/10.1109/tsmc.2020.3036879openalex-snapshot
Ensuring Cryptography Chips Security by Preventing Scan-Based Side-Channel Attacks With Improved DFT Architecture
inferred← citeshttps://doi.org/10.1109/tvlsi.2020.3023548openalex-snapshot
Automatic Floorplanning and Standalone Generation of Bitstream-Level IP Cores
inferred← citeshttps://doi.org/10.1109/tvlsi.2023.3297616openalex-snapshot
Timestamp-Based Secure Shield Architecture for Detecting Invasive Attacks
inferred← citeshttps://doi.org/10.1145/3373087.3375322openalex-snapshot
Fingerprinting Cloud FPGA Infrastructures
inferred← citeshttps://doi.org/10.1145/3394885.3431561openalex-snapshot
A Novel Technology Mapper for Complex Universal Gates
inferred← citeshttps://doi.org/10.1145/3534972openalex-snapshot
Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs
inferred← citeshttps://doi.org/10.1145/3538969.3544423openalex-snapshot
On Secure and Side-Channel Resistant Hardware Implementations of Post-Quantum Cryptography
inferred← citeshttps://doi.org/10.1145/3561515openalex-snapshot
A Survey on FPGA Cybersecurity Design Strategies
inferred← citeshttps://doi.org/10.1145/3635312openalex-snapshot
Covert-channels in FPGA-enabled SmartSSDs
inferred← citeshttps://doi.org/10.1145/3706594.3728869openalex-snapshot
Leveraging gem5 for Hardware Trojan Research: Simulation for Machine-Learning-Based Detection
inferred← citeshttps://doi.org/10.1145/3713078openalex-snapshot
Multi-Tenant Cloud FPGA: A Survey on Security, Trust, and Privacy
inferred← citeshttps://doi.org/10.1145/3761809openalex-snapshot
Timekeepers: ML-Driven SDF Analysis for Power-Wasters Detection in FPGAs
inferred← citeshttps://doi.org/10.1145/3766882.3767178openalex-snapshot
Easing the path to deployment in ML4Sys through FPGAs
inferred← citeshttps://doi.org/10.1145/3768725.3768726openalex-snapshot
CRAFT: Characterizing and Root-Causing Fault Injection Threats at Pre-Silicon
inferred← citeshttps://doi.org/10.1145/3769295openalex-snapshot
GreyConE+: Efficient Rare-Target Test Generation for FPGA HLS Designs
inferred← citeshttps://doi.org/10.1145/3801487.3801816openalex-snapshot
D3OF: DRL-Driven Dual-Layer Dynamic Obfuscation Framework for FPGAs
inferred← citeshttps://doi.org/10.1145/3848637openalex-snapshot
A Novel SRAM-based Cross-Coupled BRAM PUF Featuring Entropy-Driven Addressing for AMD FPGAs
inferred← citeshttps://doi.org/10.21203/rs.3.rs-3178414/v1openalex-snapshot
FLEX PUF: A Flexible Physical Unclonable Function Design Using Configurable Templates
inferred← citeshttps://doi.org/10.21681/2311-3456-2023-5-100-112openalex-snapshot
ON THE ONE ALGORITHMS CLASS APPLICABILITY FOR THE COMPONENTS BEHAVIOR ANALYSIS OF DEVICES WITH FIELD-PROGRAMMABLE GATE ARRAYS
inferred← citeshttps://doi.org/10.26599/tst.2019.9010048openalex-snapshot
A PUF-based and cloud-assisted lightweight authentication for multi-hop body area network
inferred← citeshttps://doi.org/10.32604/cmc.2022.020826openalex-snapshot
Efficient Autonomous Defense System Using Machine Learning on Edge Device
inferred← citeshttps://doi.org/10.32604/cmc.2023.046355openalex-snapshot
Identification of Important FPGA Modules Based on Complex Network
inferred← citeshttps://doi.org/10.3390/jlpea15040066openalex-snapshot
Research on the Security of SRAM-Based FPGAs in the Era of Artificial Intelligence
inferred← citeshttps://doi.org/10.3390/s19204598openalex-snapshot
Securing Cryptographic Chips against Scan-Based Attacks in Wireless Sensor Network Applications
inferred← citeshttps://doi.org/10.4018/979-8-3373-7267-9.ch018openalex-snapshot
Hardware Acceleration of Deep Learning for Scalable and Economically Transformative AI
inferred← citeshttps://doi.org/10.48550/arxiv.2005.04867openalex-snapshot
Security of Cloud FPGAs: A Survey
inferred← citeshttps://doi.org/10.5220/0012324200003648openalex-snapshot
Machine Learning-Based Classification of Hardware Trojans in FPGAs Implementing RISC-V Cores
inferred← citeshttps://doi.org/10.70675/a2cbf0b3zfd3bz48fczb370z5599f8519101openalex-snapshot
Etude et mise en oeuvre d'un environnement d'exécution pour architecture hétérogène reconfigurable
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Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
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