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Analytical Performance Models for NoCs with Multiple Priority Traffic Classes
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/0471791571openalex-snapshot
Queueing Networks and Markov Chains
inferredcites →https://doi.org/10.1007/s11227-009-0265-xopenalex-snapshot
Analytical modelling of networks in multicomputer systems under bursty and batch arrival traffic
inferredcites →https://doi.org/10.1016/b978-0-12-809194-4.00002-8openalex-snapshot
Knights Landing overview
inferredcites →https://doi.org/10.1016/s0166-5316(99)00075-9openalex-snapshot
Workload bounds in fluid models with priorities
inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot
Simics: A full system simulation platform
inferredcites →https://doi.org/10.1109/aspdac.2014.6742875openalex-snapshot
Bounding buffer space requirements for real-time priority-aware networks
inferredcites →https://doi.org/10.1109/date.2011.5763121openalex-snapshot
Virtual Manycore platforms: Moving towards 100+ processor cores
inferredcites →https://doi.org/10.1109/icpads.2005.93openalex-snapshot
Analysis of Discrete-Time Queues with Space and Service Priorities for Arbitrary Arrival Processes
inferredcites →https://doi.org/10.1109/ispass.2009.4919636openalex-snapshot
GARNET: A detailed on-chip network model inside a full-system simulator
inferredcites →https://doi.org/10.1109/ispass.2013.6557149openalex-snapshot
A detailed and flexible cycle-accurate Network-on-Chip simulator
inferredcites →https://doi.org/10.1109/mm.2003.1196116openalex-snapshot
The AMD opteron processor for multiprocessor servers
inferredcites →https://doi.org/10.1109/mm.2017.38openalex-snapshot
Inside 6th-Generation Intel Core: New Microarchitecture Code-Named Skylake
inferredcites →https://doi.org/10.1109/nocs.2009.5071444openalex-snapshot
Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chip
inferredcites →https://doi.org/10.1109/tc.2005.134openalex-snapshot
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
inferredcites →https://doi.org/10.1109/tc.2017.2777863openalex-snapshot
On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems
inferredcites →https://doi.org/10.1109/tcad.2010.2061613openalex-snapshot
An Analytical Approach for Network-on-Chip Performance Analysis
inferredcites →https://doi.org/10.1109/tcad.2011.2111270openalex-snapshot
Non-Stationary Traffic Analysis and Its Implications on Multicore Platform Design
inferredcites →https://doi.org/10.1109/tcad.2015.2474393openalex-snapshot
A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures
inferredcites →https://doi.org/10.1109/tcomm.2009.05.070376openalex-snapshot
Modelling and Analysis of Priority Queueing Systems with Multi-Class Self-Similar Network Traffic: A Novel and Efficient Queue-Decomposition Approach
inferredcites →https://doi.org/10.1109/tmscs.2017.2686856openalex-snapshot
ARTEMIS: An Aging-Aware Runtime Application Mapping Framework for 3D NoC-Based Chip Multiprocessors
inferredcites →https://doi.org/10.1109/tvlsi.2011.2178620openalex-snapshot
An Analytical Latency Model for Networks-on-Chip
inferredcites →https://doi.org/10.1145/1785481.1785553openalex-snapshot
A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores
inferredcites →https://doi.org/10.1145/2347655.2347669openalex-snapshot
Energy-guided exploration of on-chip network design for exa-scale computing
inferredcites →https://doi.org/10.1145/3075564.3095086openalex-snapshot
ARM HPC Ecosystem and the Reemergence of Vectors
inferredcites →https://doi.org/10.1147/rd.494.0589openalex-snapshot
Introduction to the Cell multiprocessor
inferredcites →https://doi.org/10.2307/2669582openalex-snapshot
Queueing Networks and Markov Chains: Modeling and Performance Evaluation with Computer Science Applications
inferredcites →https://doi.org/10.5120/15564-4339openalex-snapshot
Evolution of Processor Architecture in Mobile Phones
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-031-19568-6_7openalex-snapshot
In-Memory Computing for AI Accelerators: Challenges and Solutions
inferred← citeshttps://doi.org/10.1007/s11227-023-05208-0openalex-snapshot
Adaptive distribution of control messages for improving bandwidth utilization in multiple NoC
inferred← citeshttps://doi.org/10.1016/j.comcom.2021.03.002openalex-snapshot
Planning Fog networks for time-critical IoT requests
inferred← citeshttps://doi.org/10.1109/dac18072.2020.9218604openalex-snapshot
Online Adaptive Learning for Runtime Resource Management of Heterogeneous SoCs
inferred← citeshttps://doi.org/10.1109/fdl68117.2025.11165276openalex-snapshot
Performance Modeling and Analysis of Exposed Datapath Architectures
inferred← citeshttps://doi.org/10.1109/ispass64960.2025.00058openalex-snapshot
Interconnect Performance Estimation for ML Accelerators via Lightweight Analytical Model
inferred← citeshttps://doi.org/10.1109/ispass69572.2026.00019openalex-snapshot
FlexNoC: Fast and Flexible Analysis for NoCs with Arbitrary Topologies and Hybrid Arbitration
inferred← citeshttps://doi.org/10.1109/les.2020.3013003openalex-snapshot
Analytical Performance Modeling of NoCs under Priority Arbitration and Bursty Traffic
inferred← citeshttps://doi.org/10.1109/mdat.2020.3016587openalex-snapshot
Merged Logic and Memory Fabrics for Accelerating Machine Learning Workloads
inferred← citeshttps://doi.org/10.1109/mdat.2023.3310167openalex-snapshot
Fast Analysis Using Finite Queuing Model for Multilayer NoCs
inferred← citeshttps://doi.org/10.1109/tc.2020.2986963openalex-snapshot
DS3: A System-Level Domain-Specific System-on-Chip Simulation Framework
inferred← citeshttps://doi.org/10.1109/tc.2022.3191965openalex-snapshot
Traffic Characterization Based Stochastic Modelling of Network-on-Chip
inferred← citeshttps://doi.org/10.1109/tcad.2023.3251696openalex-snapshot
MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures
inferred← citeshttps://doi.org/10.1109/tvlsi.2023.3250662openalex-snapshot
Fast Performance Analysis for NoCs With Weighted Round-Robin Arbitration and Finite Buffers
inferred← citeshttps://doi.org/10.1142/s0218126624502074openalex-snapshot
Subnetwork Based Traffic Aware Rerouting for CMesh Bufferless Network-on-Chip
inferred← citeshttps://doi.org/10.1142/s0218126625504080openalex-snapshot
Performance Evaluation of a Novel EPO-FMPTMS Scheduling Technique for Balancing Traffic Patterns on NOC-Based Communication Infrastructure
inferred← citeshttps://doi.org/10.1145/3386263.3407647openalex-snapshot
MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems
inferred← citeshttps://doi.org/10.1145/3394885.3431633openalex-snapshot
Reliability-Aware Training and Performance Modeling for Processing-In-Memory Systems
inferred← citeshttps://doi.org/10.1145/3400302.3415654openalex-snapshot
Performance analysis of priority-aware NoCs with deflection routing under traffic congestion
inferred← citeshttps://doi.org/10.1145/3460233openalex-snapshot
Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks
inferred← citeshttps://doi.org/10.1145/3485434openalex-snapshot
MGait : Model-Based Gait Analysis Using Wearable Bend and Inertial Sensors
inferred← citeshttps://doi.org/10.1145/3544016openalex-snapshot
FARSI: An Early-stage Design Space Exploration Framework to Tame the Domain-specific System-on-chip Complexity
inferred← citeshttps://doi.org/10.33180/infmidem2019.402openalex-snapshot
Design of Priority Based Reconfigurable Router in Network on Chip
inferred← citeshttps://doi.org/10.70389/pjs.100117openalex-snapshot
Investigation of the Analytical Model of a Queue to Several Servers of Computer Networks with Priority Maintenance
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