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FARSI: An Early-stage Design Space Exploration Framework to Tame the Domain-specific System-on-chip Complexity
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Outgoing claims: the papers this work cites, builds on, or argues with.
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Pareto simulated annealing—a metaheuristic technique for multiple‐objective combinatorial optimization
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Application of Improved Simulated Annealing Optimization Algorithms in Hardware/Software Partitioning of the Reconfigurable System-on-Chip
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Performance and energy optimisation in CPUs through fuzzy knowledge representation
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A two-phase design space exploration strategy for system-level real-time application mapping onto MPSoC
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Efficient design space exploration for application specific systems-on-a-chip
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Automated memory-aware application distribution for Multi-processor System-on-Chips
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Exploiting domain knowledge in system-level MPSoC design space exploration
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System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search
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Equation of State Calculations by Fast Computing Machines
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MOGAC: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems
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Roofline-Model-Based Design Space Exploration for Dataflow Techniques of CNN Accelerators
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Communication-driven task binding for multiprocessor with latency insensitive network-on-chip
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Efficient symbolic multi-objective design space exploration
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Transaction level modeling: an overview
inferredcites →https://doi.org/10.1109/date.2006.243735openalex-snapshot
Efficient Design Space Exploration of High Performance Embedded Out-of-Order Processors
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Combined system synthesis and communication architecture exploration for MPSoCs
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Worst case delay analysis for memory interference in multicore systems
inferredcites →https://doi.org/10.1109/ddecs.2008.4538763openalex-snapshot
Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip
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CASSE: a system-level modeling and design-space exploration tool for multiprocessor systems-on-chip
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Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration
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Towards Exploring Vast MPSoC Mapping Design Spaces Using a Bias-Elitist Evolutionary Approach
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Hardware/software partitioning using integer programming
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NASA: A generic infrastructure for system-level MP-SoC design space exploration
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Operational mode exploration for reconfigurable systems with multiple applications
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Navigating heterogeneous processors with market mechanisms
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Strategies for anticipating risk in heterogeneous system design
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Gables: A Roofline Model for Mobile SoCs
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Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code
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ILLIXR: Enabling End-to-End Extended Reality Research
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Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors
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Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures
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SynFull: Synthetic traffic models capturing cache coherent behaviour
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Accel-Sim: An Extensible Simulation Framework for Validated GPU Modeling
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The Sky Is Not the Limit: A Visual Performance Model for Cyber-Physical Co-Design in Autonomous Machines
inferredcites →https://doi.org/10.1109/micro.2016.7783751openalex-snapshot
Co-designing accelerators and SoC interfaces using gem5-Aladdin
inferredcites →https://doi.org/10.1109/micro.2018.00054openalex-snapshot
RpStacks-MT: A High-Throughput Design Evaluation Methodology for Multi-Core Processors
inferredcites →https://doi.org/10.1109/micro50266.2020.00047openalex-snapshot
gem5-SALAM: A System Architecture for LLVM-based Accelerator Modeling
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AutoScale: Energy Efficiency Optimization for Stochastic Edge Inference Using Reinforcement Learning
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A systematic approach to exploring embedded system architectures at multiple abstraction levels
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Learning-Based Application-Agnostic 3D NoC Design for Heterogeneous Manycore Systems
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DS3: A System-Level Domain-Specific System-on-Chip Simulation Framework
inferredcites →https://doi.org/10.1109/tcad.2010.2062811openalex-snapshot
Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs
inferredcites →https://doi.org/10.1109/tevc.2005.851275openalex-snapshot
A faster algorithm for calculating hypervolume
inferredcites →https://doi.org/10.1109/tevc.2005.860766openalex-snapshot
Multiobjective optimization and evolutionary algorithms for the application mapping problem in multiprocessor system-on-chip design
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Design Space Exploration for Chiplet-Assembly-Based Processors
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A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs
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A performance analysis framework for identifying potential benefits in GPGPU applications
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A Hybrid Task Mapping Algorithm for Heterogeneous MPSoCs
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Optimizing stream program performance on CGRA-based systems
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Execution time prediction for energy-efficient hardware accelerators
inferredcites →https://doi.org/10.1145/3123939.3124541openalex-snapshot
Estimating and understanding architectural risk
inferredcites →https://doi.org/10.1145/3240765.3243483openalex-snapshot
Machine learning for design space exploration and optimization of manycore systems
inferredcites →https://doi.org/10.1145/3358176openalex-snapshot
Analytical Performance Models for NoCs with Multiple Priority Traffic Classes
inferredcites →https://doi.org/10.1145/3529257openalex-snapshot
CEDR: A Compiler-integrated, Extensible DSSoC Runtime
inferredcites →https://doi.org/10.1145/371636.371690openalex-snapshot
Development cost and size estimation starting from high-level specifications
inferredcites →https://doi.org/10.1145/502059.502045openalex-snapshot
Managing energy and server resources in hosting centers
inferredcites →https://doi.org/10.1145/774789.774804openalex-snapshot
Multi-objective design space exploration using genetic algorithms
inferredcites →https://doi.org/10.1155/2008/280347openalex-snapshot
A Priori Implementation Effort Estimation for Hardware Design Based on Independent Path Analysis
inferredcites →https://doi.org/10.1155/2015/157305openalex-snapshot
Automated Design Space Exploration with Aspen
inferredcites →https://doi.org/10.11591/eecsi.v1.352openalex-snapshot
Energy-Aware Network-on-Chip Application Mapping Based on Domain Knowledge Genetic Algorithm
inferredcites →https://doi.org/10.23919/date.2018.8341997openalex-snapshot
DS-DSE: Domain-specific design space exploration for streaming applications
inferredcites →https://doi.org/10.48550/arxiv.2007.14371openalex-snapshot
STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors
inferredcites →https://doi.org/10.7873/date.2014.020openalex-snapshot
Multi-variant-based design space exploration for automotive embedded systems
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cpe.8318openalex-snapshot
A Survey on Heterogeneous CPU–GPU Architectures and Simulators
inferred← citeshttps://doi.org/10.1016/j.sysarc.2026.103891openalex-snapshot
Cooperative game-theoretic runtime prediction and contention-aware partitioning for heterogeneous embedded systems
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Evaluation and validation of efficient hierarchical interconnection in multi-processor system on chip
inferred← citeshttps://doi.org/10.1109/access.2024.3365632openalex-snapshot
Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey
inferred← citeshttps://doi.org/10.1109/asp-dac66049.2026.11420537openalex-snapshot
NetTLM-DSE: Design Space Exploration for DNN Layer-Pipeline Spatial Mappings
inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00100openalex-snapshot
ARTEMIS: Agile Discovery of Efficient Real-Time Systems-on-Chips in the Heterogeneous Era
inferred← citeshttps://doi.org/10.1109/iiswc66894.2025.00044openalex-snapshot
XRSight: An End-to-End Hardware-Software Co-Design Platform for XR SoC Evaluation
inferred← citeshttps://doi.org/10.1109/iiswc66894.2025.00045openalex-snapshot
Icicle: Open-Source Hardware Support for Top-Down Microarchitectural Analysis on RISC-V
inferred← citeshttps://doi.org/10.1109/iscas56072.2025.11043244openalex-snapshot
Stream-Driven Acceleration for Embedded RISC-V SoCs
inferred← citeshttps://doi.org/10.1109/jetcas.2025.3590065openalex-snapshot
Cool-3D: An End-to-End Thermal-Aware Framework for Early-Phase Design Space Exploration of Microfluidic-Cooled 3DICs
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Domain-Specific Architectures: Research Problems and Promising Approaches
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ArchGym: An Open-Source Gymnasium for Machine Learning Assisted Architecture Design
inferred← citeshttps://doi.org/10.1145/3626774openalex-snapshot
Agents of Autonomy: A Systematic Study of Robotics on Modern Hardware
inferred← citeshttps://doi.org/10.1145/3696952.3696962openalex-snapshot
Performance Study of Intelligent Monitoring System for Power Plant Based on UWB
inferred← citeshttps://doi.org/10.1145/3721145.3729518openalex-snapshot
HARNESS: Holistic Resource Management for Diversely Scaled Edge Cloud Systems
inferred← citeshttps://doi.org/10.1145/3760257openalex-snapshot
RIMMS: Runtime Integrated Memory Management System for Heterogeneous Computing
inferred← citeshttps://doi.org/10.1145/3770080openalex-snapshot
Toward Comprehensive Design Space Exploration on Heterogeneous Multi-core Processors
inferred← citeshttps://doi.org/10.48084/etasr.17963openalex-snapshot
Boosting WLAN Performance Using a Hybrid Network-on-Chip Routing Architecture with Predictive Congestion Avoidance
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