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Informed Prefetching for Indirect Memory Accesses

https://doi.org/10.1145/3374216
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-0-387-09766-4_133openalex-snapshot
NAS Parallel Benchmarks
inferredcites →https://doi.org/10.1007/978-3-319-63390-9_2openalex-snapshot
Ascertaining Uncertainty for Efficient Exact Cache Analysis
inferredcites →https://doi.org/10.1109/12.381947openalex-snapshot
Effective hardware-based data prefetching for high-performance processors
inferredcites →https://doi.org/10.1109/hpca.2009.4798239openalex-snapshot
Practical off-chip meta-data for temporal memory streaming
inferredcites →https://doi.org/10.1109/iiswc.2008.4636095openalex-snapshot
Temporal streams in commercial server applications
inferredcites →https://doi.org/10.1109/tc.2004.1261824openalex-snapshot
A prefetch taxonomy
inferredcites →https://doi.org/10.1137/0214017openalex-snapshot
Arboricity and Subgraph Listing Algorithms
inferredcites →https://doi.org/10.1145/106975.106979openalex-snapshot
Software prefetching
inferredcites →https://doi.org/10.1145/1080695.1069989openalex-snapshot
Temporal Streaming of Shared Memory
inferredcites →https://doi.org/10.1145/125826openalex-snapshot
Proceedings of the 1991 ACM/IEEE conference on Supercomputing - Supercomputing '91
inferredcites →https://doi.org/10.1145/1273440.1250696openalex-snapshot
Mechanisms for store-wait-free multiprocessors
inferredcites →https://doi.org/10.1145/1555815.1555766openalex-snapshot
Spatio-temporal memory streaming
inferredcites →https://doi.org/10.1145/192007.192014openalex-snapshot
Evaluating stream buffers as a secondary cache replacement
inferredcites →https://doi.org/10.1145/2024716.2024718openalex-snapshot
The gem5 simulator
inferredcites →https://doi.org/10.1145/2133382.2133384openalex-snapshot
When Prefetching Works, When It Doesn’t, and Why
inferredcites →https://doi.org/10.1145/216585.216588openalex-snapshot
Hitting the memory wall
inferredcites →https://doi.org/10.1145/248208.237190openalex-snapshot
Compiler-based prefetching for recursive data structures
inferredcites →https://doi.org/10.1145/2830772.2830807openalex-snapshot
IMP
inferredcites →https://doi.org/10.1145/30350openalex-snapshot
Proceedings of the 14th annual international symposium on Computer architecture - ISCA '87
inferredcites →https://doi.org/10.1145/325096.325162openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
inferredcites →https://doi.org/10.1145/3296957.3173189openalex-snapshot
An Event-Triggered Programmable Prefetcher for Irregular Workloads
inferredcites →https://doi.org/10.1145/358923.358939openalex-snapshot
Data prefetch mechanisms
inferredcites →https://doi.org/10.1145/379240.379250openalex-snapshot
Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors
inferredcites →https://doi.org/10.1145/384265.291034openalex-snapshot
Dependence based prefetching for linked data structures
inferredcites →https://doi.org/10.1145/605397.605427openalex-snapshot
A stateless, content-directed data prefetching mechanism
inferredcites →https://doi.org/10.1145/605432.605415openalex-snapshot
Design and evaluation of compiler algorithms for pre-execution
inferredcites →https://doi.org/10.1147/rd.491.0127openalex-snapshot
Exploring the limits of prefetching

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1016/j.future.2024.03.012openalex-snapshot
A prefetching indexing scheme for in-memory database systems
inferred← citeshttps://doi.org/10.1109/access.2021.3123379openalex-snapshot
A Performance Evaluation of DRAM Access for In-Memory Databases
inferred← citeshttps://doi.org/10.1109/access.2022.3195046openalex-snapshot
A Cross-Prefetcher Schedule Optimization Methodology
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00040openalex-snapshot
Differential-Matching Prefetcher for Indirect Memory Access
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00024openalex-snapshot
Vector Runahead
inferred← citeshttps://doi.org/10.1109/sp61157.2025.00023openalex-snapshot
Peek-a-Walk: Leaking Secrets via Page Walk Side Channels
inferred← citeshttps://doi.org/10.1109/tcad.2023.3335880openalex-snapshot
PDG: A Prefetcher for Dynamic Graph Updating
inferred← citeshttps://doi.org/10.1145/3452099openalex-snapshot
Fast Key-Value Lookups with Node Tracker
inferred← citeshttps://doi.org/10.1145/3613424.3614255openalex-snapshot
Decoupled Vector Runahead
inferred← citeshttps://doi.org/10.1145/3641853openalex-snapshot
Tyche: An Efficient and General Prefetcher for Indirect Memory Accesses
inferred← citeshttps://doi.org/10.1145/3676861openalex-snapshot
FAJITA: Stateful Packet Processing at 100 Million pps
inferred← citeshttps://doi.org/10.54097/yd6k8n48openalex-snapshot
When AI Meets Cache: Intelligent Memory Hierarchy Management in Modern CPUs
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