On the public citation graph
Voltage-Based Covert Channels Using FPGAs
0 signed · 66 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-642-04138-9_27openalex-snapshot
Trojan Side-Channels: Lightweight Hardware Trojans through Side-Channel Engineering
inferredcites →https://doi.org/10.1049/el.2019.0163openalex-snapshot
Oscillator without a combinatorial loop and its threat to FPGA in data centre
inferredcites →https://doi.org/10.1109/acsac.2006.20openalex-snapshot
Covert and Side Channels Due to Processor Architecture
inferredcites →https://doi.org/10.1109/cloudcom.2015.60openalex-snapshot
Virtualized FPGA Accelerators for Efficient Cloud Computing
inferredcites →https://doi.org/10.1109/fccm.2010.43openalex-snapshot
Using the Power Side Channel of FPGAs for Communication
inferredcites →https://doi.org/10.1109/fccm.2014.42openalex-snapshot
FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStack
inferredcites →https://doi.org/10.1109/fpl.2012.6339242openalex-snapshot
FPGAs for trusted cloud computing
inferredcites →https://doi.org/10.1109/iscas.1989.100747openalex-snapshot
Combinational profiles of sequential benchmark circuits
inferredcites →https://doi.org/10.1109/lca.2018.2860006openalex-snapshot
A New Class of Covert Channels Exploiting Power Management Vulnerabilities
inferredcites →https://doi.org/10.1109/mdt.2007.79openalex-snapshot
Power Supply Noise in SoCs: Metrics, Management, and Measurement
inferredcites →https://doi.org/10.1109/mdt.2010.7openalex-snapshot
A Survey of Hardware Trojan Taxonomy and Detection
inferredcites →https://doi.org/10.1109/mitp.2023.3246667openalex-snapshot
IEEE Symposium on Security and Privacy
inferredcites →https://doi.org/10.1109/recosoc.2011.5981510openalex-snapshot
Temperature-based covert channel in FPGA systems
inferredcites →https://doi.org/10.1109/sp.2007.28openalex-snapshot
Moats and Drawbridges: An Isolation Primitive for Reconfigurable Hardware Based Systems
inferredcites →https://doi.org/10.1109/sp.2019.00002openalex-snapshot
Spectre Attacks: Exploiting Speculative Execution
inferredcites →https://doi.org/10.1109/tie.2018.2808907openalex-snapshot
Frequency-Domain Power Delivery Network Self-Characterization in FPGAs for Improved System Reliability
inferredcites →https://doi.org/10.1109/tifs.2019.2952257openalex-snapshot
PowerHammer: Exfiltrating Data From Air-Gapped Computers Through Power Lines
inferredcites →https://doi.org/10.1109/tvlsi.2004.825834openalex-snapshot
Scaling trends of on-chip power distribution noise
inferredcites →https://doi.org/10.1109/tvlsi.2018.2848460openalex-snapshot
An Experimental Evaluation and Analysis of Transient Voltage Fluctuations in FPGAs
inferredcites →https://doi.org/10.1145/2133352.2133353openalex-snapshot
Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems
inferredcites →https://doi.org/10.1145/2435264.2435283openalex-snapshot
Sensing nanosecond-scale voltage attacks and natural transients in FPGAs
inferredcites →https://doi.org/10.1145/2678373.2665678openalex-snapshot
A reconfigurable fabric for accelerating large-scale datacenter services
inferredcites →https://doi.org/10.1145/3240765.3240841openalex-snapshot
Remote inter-chip power analysis side-channel attacks at board-level
inferredcites →https://doi.org/10.1145/3289602.3293920openalex-snapshot
Temporal Thermal Covert Channels in Cloud FPGAs
inferredcites →https://doi.org/10.1145/3289602.3293923openalex-snapshot
Characterization of Long Wire Data Leakage in Deep Submicron FPGAs
inferredcites →https://doi.org/10.1145/3328222openalex-snapshot
Mitigating Electrical-level Attacks towards Secure Multi-Tenant FPGAs in the Cloud
inferredcites →https://doi.org/10.23919/date.2018.8342177openalex-snapshot
An inside job: Remote power analysis attacks on FPGAs
inferredcites →https://doi.org/10.46586/tches.v2018.i3.44-68openalex-snapshot
FPGAhammer: Remote Voltage Fault Attacks on Shared FPGAs, suitable for DFA on AES
inferredcites →https://doi.org/10.48550/arxiv.1612.04474openalex-snapshot
Your Processor Leaks Information - and There's Nothing You Can Do About It
inferredcites →https://doi.org/10.5555/3291168.3291177openalex-snapshot
Sharing, protection, and compatibility for reconfigurable fabric with Amorphos
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-031-45395-3_5openalex-snapshot
Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs
inferred← citeshttps://doi.org/10.1007/s11227-025-07340-5openalex-snapshot
Toward secure program execution in multi-tenant cloud FPGA environments
inferred← citeshttps://doi.org/10.1007/s41635-023-00135-1openalex-snapshot
Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs
inferred← citeshttps://doi.org/10.1007/s41635-024-00155-5openalex-snapshot
High-Confidence Remote Power Analysis on Heterogeneous SoCs
inferred← citeshttps://doi.org/10.1109/access.2023.3261802openalex-snapshot
A Survey of Trusted Computing Solutions Using FPGAs
inferred← citeshttps://doi.org/10.1109/asianhost59942.2023.10409377openalex-snapshot
Emulating Covert Data Transmission on Heterogeneous SoCs
inferred← citeshttps://doi.org/10.1109/dac63849.2025.11132492openalex-snapshot
LeakyDSP: Exploiting Digital Signal Processing Blocks to Sense Voltage Fluctuations in FPGAs
inferred← citeshttps://doi.org/10.1109/dac63849.2025.11133099openalex-snapshot
A Novel Covert Timing Channel for Cloud FPGAs
inferred← citeshttps://doi.org/10.1109/eurospw59978.2023.00036openalex-snapshot
Emulating Side Channel Attacks on gem5: lessons learned
inferred← citeshttps://doi.org/10.1109/host55118.2023.10133626openalex-snapshot
Advanced Covert-Channels in Modern SoCs
inferred← citeshttps://doi.org/10.1109/host55342.2024.10545396openalex-snapshot
Resurrection Attack: Defeating Xilinx MPU's Memory Protection
inferred← citeshttps://doi.org/10.1109/iscas56072.2025.11043441openalex-snapshot
On-die Differential Sensing for Monitoring and Analysis of Dynamic Computing Environments
inferred← citeshttps://doi.org/10.1109/jproc.2023.3330729openalex-snapshot
A Visionary Look at the Security of Reconfigurable Cloud Computing
inferred← citeshttps://doi.org/10.1109/tc.2026.3700805openalex-snapshot
Voltage Channel: Exploiting GPU Voltage Noise for Covert and Side Channel Attacks
inferred← citeshttps://doi.org/10.1109/tcad.2021.3059245openalex-snapshot
Detection of and Countermeasure Against Thermal Covert Channel in Many-Core Systems
inferred← citeshttps://doi.org/10.1109/tcsi.2024.3413364openalex-snapshot
Efficient Adaptive Multi-Level Privilege Partitioning With RTrustSoC
inferred← citeshttps://doi.org/10.1109/tcsi.2024.3435841openalex-snapshot
Power and Frequency Intrinsic Channels on gem5
inferred← citeshttps://doi.org/10.1109/tdsc.2025.3550568openalex-snapshot
A Covert and Efficient Attack on FPGA Cloud Based on Adaptive RON
inferred← citeshttps://doi.org/10.1109/tetc.2021.3115176openalex-snapshot
PUFs Physical Learning: Accelerating the Enrollment via Delay-Based Model Extraction
inferred← citeshttps://doi.org/10.1109/trustcom60117.2023.00259openalex-snapshot
A Near-Field EM Sensor Implemented in FPGA Configurable Fabric
inferred← citeshttps://doi.org/10.1145/3561515openalex-snapshot
A Survey on FPGA Cybersecurity Design Strategies
inferred← citeshttps://doi.org/10.1145/3620665.3640355openalex-snapshot
Pentimento: Data Remanence in Cloud FPGAs
inferred← citeshttps://doi.org/10.1145/3658617.3697767openalex-snapshot
Through Fabric: A Cross-world Thermal Covert Channel on TEE-enhanced FPGA-MPSoC Systems
inferred← citeshttps://doi.org/10.1145/3676536.3676843openalex-snapshot
DoS-FPGA: Denial of Service on Cloud FPGAs via Coordinated Power Hammering
inferred← citeshttps://doi.org/10.1145/3676641.3716012openalex-snapshot
PhasePrint: Exposing Cloud FPGA Fingerprints by Inducing Timing Faults at Runtime
inferred← citeshttps://doi.org/10.1145/3779437openalex-snapshot
Novel Security Threats in Multi-Tenant FPGAs: Phase Tuning for Voltage Sensors in Remote Power Side-Channel Analysis Attacks on AES
inferred← citeshttps://doi.org/10.23919/date64628.2025.10992759openalex-snapshot
Three Eyed Raven: An On-Chip Side Channel Analysis Framework for Run-Time Evaluation
inferred← citeshttps://doi.org/10.3390/s23042081openalex-snapshot
Covert Channel Communication as an Emerging Security Threat in 2.5D/3D Integrated Systems
inferred← citeshttps://doi.org/10.3390/s25154861openalex-snapshot
ChipletQuake: On-Die Digital Impedance Sensing for Chiplet and Interposer Verification
inferred← citeshttps://doi.org/10.46586/tches.v2023.i2.543-567openalex-snapshot
RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks
inferred← citeshttps://doi.org/10.70675/0fc3d40bz6a38z4c78z9a9cz4958577081bbopenalex-snapshot
Optimizing data leakage exploitation in the context of screamingchannel attacks
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.